[llvm] [AArch64][CostModel] Consider i32 --> i64 partial reduce cost as Invalid for FixedLength vectors (PR #165226)

[Sushant Gokhale via llvm-commits]

================
@@ -5757,8 +5757,15 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
       return Cost;
   }
 
+  if (!ST->useSVEForFixedLengthVectors() &&
+      (AccumLT.second.isFixedLengthVector() && ST->isNeonAvailable() &&
+       ST->hasDotProd()) &&
+      (AccumLT.second.getScalarType() == MVT::i64 &&
+       InputLT.second.getScalarType() == MVT::i32))
+    return Invalid;
----------------
sushgokh wrote:

If I prevent this Neon to SVE lowering, it creates dependencies 
v0 from saddw --> v0 of saddw2

in the code 
```
saddw	v0.2d, v0.2d, v1.2s
saddw2	v0.2d, v0.2d, v1.4s
```

Now resolving this at codegen level is difficult because of :
In the code for state T1, 2 phi's are added in the vector body as against 1 for the above code. If we try to change this so that different regs are used for both instructions, we are essentially resorting to code in state T1

https://github.com/llvm/llvm-project/pull/165226