[llvm] [SelectionDAG] Widen <2 x T> vector types for atomic load (PR #148897)

[Simon Pilgrim via llvm-commits]

================
@@ -6248,6 +6251,72 @@ SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
                      N->getOperand(1), N->getOperand(2));
 }
 
+/// Either return the same load or provide appropriate casts
+/// from the load and return that.
+static SDValue coerceLoadedValue(SDValue LdOp, EVT FirstVT, EVT WidenVT,
+                                 TypeSize LdWidth, TypeSize FirstVTWidth,
+                                 SDLoc dl, SelectionDAG &DAG) {
+  assert(TypeSize::isKnownLE(LdWidth, FirstVTWidth));
----------------
RKSimon wrote:

(style) missing assert message

https://github.com/llvm/llvm-project/pull/148897