[llvm] [GlobalISel] Implement G_UADDO/G_UADDE/G_SADDO/G_SADDE for computeKnownBits (PR #165497)

[Yatao Wang via llvm-commits]

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@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name:            CstCarryInZeroOutZero
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CstCarryInZeroOutZero
+  ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+  ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+  ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+  ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+  ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+    %0:_(s8) = G_CONSTANT i8 2
+    %1:_(s8) = G_CONSTANT i8 24
+    %2:_(s1) = G_CONSTANT i1 0
+    %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name:            CstCarryInOneOutZero
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CstCarryInOneOutZero
+  ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+  ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+  ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+  ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+  ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+    %0:_(s8) = G_CONSTANT i8 2
+    %1:_(s8) = G_CONSTANT i8 24
+    %2:_(s1) = G_CONSTANT i1 1
+    %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name:            CstCarryInZeroOutOne
+body:             |
+  bb.1:
+  ; CHECK-LABEL: name: @CstCarryInZeroOutOne
+  ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+  ; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
+  ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+  ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+  ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
----------------
ningxinr wrote:

Is this expected for `SADD[OE]`? I thought in this case we should have the carry out bit set to one instead of overflowing. Something looks like the following:
```suggestion
  ; CHECK-NEXT: %3:_ KnownBits:00000001 SignBits:1
  ; CHECK-NEXT: %4:_ KnownBits:1 SignBits:1
```

Also, the same behavior can be reproduced for `SADDO_CARRY` in `SelectionDAG`. Plus, I couldn't seem to figure out how `KnownBits::computeForAddCarry` differentiate add for signed int or unsigned int. Am I missing something here?

https://github.com/llvm/llvm-project/pull/165497