[llvm] [GlobalISel] Implement G_UADDO/G_UADDE/G_SADDO/G_SADDE for computeKnownBits (PR #165497)
Yatao Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 28 18:49:33 PDT 2025
https://github.com/ningxinr created https://github.com/llvm/llvm-project/pull/165497
This is a draft PR addressing the carry out cases Matt mentioned in #159202.
TODO: Add more tests once I can confirm that this is on the right track. G_[US]SUB[OE] will be implemented in a different PR.
>From 5a117b2af4b69f19e7b2c860877657e2f85a2380 Mon Sep 17 00:00:00 2001
From: ningxinr <ningxinr at live.cn>
Date: Wed, 22 Oct 2025 14:21:01 -0700
Subject: [PATCH] [GlobalISel] Implement G_UADDO/G_UADDE/G_SADDO/G_SADDE for
computeKnownBits
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 32 +++++++++-
.../AArch64/GlobalISel/knownbits-sadde.mir | 63 +++++++++++++++++++
.../AArch64/GlobalISel/knownbits-saddo.mir | 29 +++++++++
.../AArch64/GlobalISel/knownbits-uadde.mir | 63 +++++++++++++++++++
.../AArch64/GlobalISel/knownbits-uaddo.mir | 29 +++++++++
.../legalize-trailing-zeros-undef.mir | 6 +-
.../GlobalISel/legalize-trailing-zeros.mir | 6 +-
7 files changed, 217 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index d6f23b62519fe..2a844ee0f9fcf 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -615,7 +615,37 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
case TargetOpcode::G_UADDO:
case TargetOpcode::G_UADDE:
case TargetOpcode::G_SADDO:
- case TargetOpcode::G_SADDE:
+ case TargetOpcode::G_SADDE: {
+ if (MI.getOperand(1).getReg() == R) {
+ // If we know the result of a compare has the top bits zero, use this
+ // info.
+ if (TL.getBooleanContents(DstTy.isVector(), false) ==
+ TargetLowering::ZeroOrOneBooleanContent &&
+ BitWidth > 1)
+ Known.Zero.setBitsFrom(1);
+ break;
+ }
+
+ assert(MI.getOperand(0).getReg() == R &&
+ "We only compute knownbits for the sum here.");
+ // With UADDO_CARRY, a carry bit may be added in.
+ KnownBits Carry(1);
+ if (Opcode == TargetOpcode::G_UADDE || Opcode == TargetOpcode::G_SADDE) {
+ computeKnownBitsImpl(MI.getOperand(4).getReg(), Known, DemandedElts,
+ Depth + 1);
+ // Carry has bit width 1
+ Carry = Carry.trunc(1);
+ } else {
+ Carry.setAllZero();
+ }
+
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(3).getReg(), Known2, DemandedElts,
+ Depth + 1);
+ Known = KnownBits::computeForAddCarry(Known, Known2, Carry);
+ break;
+ }
case TargetOpcode::G_USUBO:
case TargetOpcode::G_USUBE:
case TargetOpcode::G_SSUBO:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
new file mode 100644
index 0000000000000..be1777cae827b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sadde.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryInZeroOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name: CstCarryInZeroOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 127
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:01111111 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:100000?? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 127
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_SADDE %0, %1, %2
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
new file mode 100644
index 0000000000000..40c7e25ab943a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-saddo.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:00011010 SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s8), %3:_(s1) = G_SADDO %0, %1
+...
+---
+name: CstCarryOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:01111110 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:10000000 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 126
+ %2:_(s8), %3:_(s1) = G_SADDO %0, %1
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
new file mode 100644
index 0000000000000..6f2aa10a1115a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uadde.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryInZeroOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:0001101? SignBits:3
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
+---
+name: CstCarryInZeroOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInZeroOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:0 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 255
+ %2:_(s1) = G_CONSTANT i1 0
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
+---
+name: CstCarryInOneOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryInOneOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8
+ ; CHECK-NEXT: %2:_ KnownBits:1 SignBits:1
+ ; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
+ ; CHECK-NEXT: %4:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 255
+ %2:_(s1) = G_CONSTANT i1 1
+ %3:_(s8), %4:_(s1) = G_UADDE %0, %1, %2
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
new file mode 100644
index 0000000000000..b10ea6c2926b3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-uaddo.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: CstCarryOutZero
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutZero
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:00011000 SignBits:3
+ ; CHECK-NEXT: %2:_ KnownBits:00011010 SignBits:3
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 24
+ %2:_(s8), %4:_(s1) = G_UADDO %0, %1
+...
+---
+name: CstCarryOutOne
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstCarryOutOne
+ ; CHECK-NEXT: %0:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %1:_ KnownBits:11111110 SignBits:7
+ ; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
+ ; CHECK-NEXT: %3:_ KnownBits:? SignBits:1
+ %0:_(s8) = G_CONSTANT i8 2
+ %1:_(s8) = G_CONSTANT i8 254
+ %2:_(s8), %4:_(s1) = G_UADDO %0, %1
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
index 57e729fb03ab6..8255e01d71864 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
@@ -40,11 +40,7 @@ body: |
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
- ; X86-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; X86-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C4]]
- ; X86-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C5]]
- ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[AND2]](s32)
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: RET 0, implicit [[MV]](s64)
%0(s64) = COPY $rdx
%1:_(s35) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
index f5d847776ec06..a429e89e8f255 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
@@ -40,11 +40,7 @@ body: |
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; X86-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDO]], [[CTTZ_ZERO_UNDEF1]]
; X86-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[UADDE]], [[C]]
- ; X86-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; X86-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C4]]
- ; X86-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C5]]
- ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND1]](s32), [[AND2]](s32)
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
; X86-NEXT: RET 0, implicit [[MV]](s64)
%0(s64) = COPY $rdx
%1:_(s35) = G_TRUNC %0(s64)
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