[llvm] [RISCV] Add short forward branch support for `min`, `max`, `maxu` and `minu` (PR #164394)

[Sam Elliott via llvm-commits]

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@@ -1739,14 +1739,21 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
 /// return the defining instruction.
 static MachineInstr *canFoldAsPredicatedOp(Register Reg,
                                            const MachineRegisterInfo &MRI,
-                                           const TargetInstrInfo *TII) {
+                                           const TargetInstrInfo *TII,
+                                           bool minmax) {
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lenary wrote:

It's clearer if you pass a `const RISCVSubtarget &STI` here and do the `STI.hasShortForwardBranchIMinMax()` in the `if`.

https://github.com/llvm/llvm-project/pull/164394