[llvm] [WIP][AMDGPU][MC] Support 128b rsrc reg in mimg instructions (PR #139121)

[Mirko Brkušanin via llvm-commits]

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@@ -922,6 +922,15 @@ defm "" : SRegClass<16, Reg512Types.types, SGPR_512Regs, TTMP_512Regs>;
 defm "" : SRegClass<32, Reg1024Types.types, SGPR_1024Regs>;
 }
 
+def SReg_RSRC : SIRegisterClass<"AMDGPU", [v8i32], 32,
+  (add SReg_256_XNULL, SReg_128_XNULL)> {
+  let Size = 8;
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mbrkusanin wrote:

Doesn't this imply that a value of type v8i32 can be stored in a SReg_128_XNULL register?
Also "Size" is in bits, but if you have both SReg256 and SReg128 I'm not sure what to set.

I do not see any codegen tests with the new 128 rsrc size. This definition in fine for assembler/disassembler parts but I'm not sure if this works for codegen so please try some tests.

We've tried before to use a custom RegisterClass with registers of different sizes and run into an issue where codegen would sometimes pick wrong register class. That case however had a mix of SGPRs and VGPRs.

https://github.com/llvm/llvm-project/pull/139121