[llvm] [AMDGPU][AsmParser]: Use dummy operand for parsing buffer_ SWZ operand. (PR #165305)
Jeffrey Byrnes via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 27 12:36:07 PDT 2025
https://github.com/jrbyrnes created https://github.com/llvm/llvm-project/pull/165305
`MCInstrDesc` counts the SWZ operand for `NumOperands` -- thus, since we do not parse this into the `MCInst` operands, there will be a mismatch between `MCInst.getNumOperands` and `MCInstrDesc.getNumOperands` .
`llvm-mca` assumes that each operand counted by `MCInstrDesc.getNumOperands` will be present in `MCInst.operands` https://github.com/llvm/llvm-project/blob/263377a17570e1cbe6eeae9ffa5ce02f240839ef/llvm/lib/MCA/InstrBuilder.cpp#L324
This parses a dummy operand for the buffer_loads as a placeholder for the implicit SWZ operand. This is similar to the parsing of `tbuffer_` variants which automatically parse the dummy operand https://github.com/llvm/llvm-project/blob/263377a17570e1cbe6eeae9ffa5ce02f240839ef/llvm/utils/TableGen/AsmMatcherEmitter.cpp#L1853
>From a1e811fb851ad183f43c3596b533ed19c20a3bf2 Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Mon, 27 Oct 2025 12:08:00 -0700
Subject: [PATCH] [AMDGPU][AsmParser]: Use dummy operand for parsing buffer_
SWZ operand.
Change-Id: I7866559e3fe3aad4158d658580d328a5aac2b423
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 3 ++
llvm/test/MC/AMDGPU/buffer-op-swz-operand.s | 43 ++++++++++++++++++
.../llvm-mca/AMDGPU/buffer-op-swz-operand.s | 45 +++++++++++++++++++
3 files changed, 91 insertions(+)
create mode 100644 llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
create mode 100644 llvm/test/tools/llvm-mca/AMDGPU/buffer-op-swz-operand.s
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 99ba04378ba2e..97eeaaae6ce44 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -9048,6 +9048,9 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
+ // Parse a dummy operand as a placeholder for the SWZ operand. This enforces
+ // agreement between MCInstrDesc.getNumOperands and MCInst.getNumOperands.
+ Inst.addOperand(MCOperand::createImm(0));
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
new file mode 100644
index 0000000000000..8bd91484d149c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
@@ -0,0 +1,43 @@
+// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1100 --show-inst < %s | FileCheck %s
+
+// CHECK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
+buffer_load_dwordx4 v[0:3], v0, s[0:3], 0, offen offset:4092 slc
+// CHECK: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4092 slc ; <MCInst #13135 BUFFER_LOAD_DWORDX4_OFFEN_gfx11
+// CHECK-NEXT: ; <MCOperand Reg:10104>
+// CHECK-NEXT: ; <MCOperand Reg:486>
+// CHECK-NEXT: ; <MCOperand Reg:7754>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:4092>
+// CHECK-NEXT: ; <MCOperand Imm:2>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
+buffer_store_dword v0, v1, s[0:3], 0 offen slc
+// CHECK: buffer_store_b32 v0, v1, s[0:3], 0 offen slc ; <MCInst #14553 BUFFER_STORE_DWORD_OFFEN_gfx11
+// CHECK-NEXT: ; <MCOperand Reg:486>
+// CHECK-NEXT: ; <MCOperand Reg:487>
+// CHECK-NEXT: ; <MCOperand Reg:7754>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:2>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
+
+; tbuffer ops use autogenerate asm parsers
+tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc
+// CHECK: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_FMT_32_32_SINT] offen offset:4092 slc ; <MCInst #34095 TBUFFER_LOAD_FORMAT_XYZW_OFFEN_gfx11
+// CHECK-NEXT: ; <MCOperand Reg:10104>
+// CHECK-NEXT: ; <MCOperand Reg:486>
+// CHECK-NEXT: ; <MCOperand Reg:7754>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:4092>
+// CHECK-NEXT: ; <MCOperand Imm:49>
+// CHECK-NEXT: ; <MCOperand Imm:2>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
+tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc
+// CHECK: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] offen slc ; <MCInst #34264 TBUFFER_STORE_FORMAT_D16_X_OFFEN_gfx11
+// CHECK-NEXT: ; <MCOperand Reg:486>
+// CHECK-NEXT: ; <MCOperand Reg:487>
+// CHECK-NEXT: ; <MCOperand Reg:7754>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:0>
+// CHECK-NEXT: ; <MCOperand Imm:33>
+// CHECK-NEXT: ; <MCOperand Imm:2>
+// CHECK-NEXT: ; <MCOperand Imm:0>>
diff --git a/llvm/test/tools/llvm-mca/AMDGPU/buffer-op-swz-operand.s b/llvm/test/tools/llvm-mca/AMDGPU/buffer-op-swz-operand.s
new file mode 100644
index 0000000000000..932d9d1cc48b5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AMDGPU/buffer-op-swz-operand.s
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s
+
+buffer_load_dwordx4 v[30:33], v4, s[0:3], 0, offen offset:4092
+buffer_store_dword v0, v1, s[0:3], 0 offen
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 200
+# CHECK-NEXT: Total Cycles: 280
+# CHECK-NEXT: Total uOps: 200
+
+# CHECK: Dispatch Width: 1
+# CHECK-NEXT: uOps Per Cycle: 0.71
+# CHECK-NEXT: IPC: 0.71
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 80 1.00 * U buffer_load_dwordx4 v[30:33], v4, s[0:3], 0 offen offset:4092
+# CHECK-NEXT: 1 80 1.00 * U buffer_store_dword v0, v1, s[0:3], 0 offen
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - HWBranch
+# CHECK-NEXT: [1] - HWExport
+# CHECK-NEXT: [2] - HWLGKM
+# CHECK-NEXT: [3] - HWSALU
+# CHECK-NEXT: [4] - HWVALU
+# CHECK-NEXT: [5] - HWVMEM
+# CHECK-NEXT: [6] - HWXDL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6]
+# CHECK-NEXT: - - - - - 2.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - buffer_load_dwordx4 v[30:33], v4, s[0:3], 0 offen offset:4092
+# CHECK-NEXT: - - - - - 1.00 - buffer_store_dword v0, v1, s[0:3], 0 offen
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