[llvm] [RISCV] 'Zalrsc' may permit non-base instructions (PR #165042)
Francesco Petrogalli via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 27 09:40:53 PDT 2025
================
@@ -682,6 +702,9 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
MachineBasicBlock::iterator &NextMBBI) {
+ // Using MIN(U)/MAX(U) is preferrable if permitted
+ if (STI->hasPermissiveZalrsc() && STI->hasStdExtZbb() && !IsMasked)
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fpetrogalli wrote:
I won't hold the patch on this, it is up to you, I find them very useful not just for helping debugging, but also to understand the intention of the code.
https://github.com/llvm/llvm-project/pull/165042
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