[llvm] [RISCV] Support P extension ABSW instruction. (PR #165047)

[Brandon Wu via llvm-commits]

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@@ -21862,6 +21873,7 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
   case RISCVISD::REMUW:
   case RISCVISD::ROLW:
   case RISCVISD::RORW:
+  case RISCVISD::ABSW:
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4vtomat wrote:

As per spec, I think only first 32 bits are read~

https://github.com/llvm/llvm-project/pull/165047