[llvm] [GlobalISel] Rename G_ABDS/G_ABDU to G_SABD/G_UABD (PR #165236)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 27 04:11:25 PDT 2025
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/165236
All the other opcodes in GISel put the signed/unsigned at the start of the opcode name, including UMULH which is MULHU in SDAG. Do the same for G_UABD and G_SABD to keep them consistent with other nodes.
>From 4da7ecdae10d304f03f717099d470d55f35cd6aa Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 27 Oct 2025 11:08:50 +0000
Subject: [PATCH] [GlobalISel] Rename G_ABDS/G_ABDU to G_SABD/G_UABD
All the other opcodes in GISel put the signed/unsigned at the start of the
opcode name, including UMULH which is MULHU in SDAG. Do the same for G_UABD and
G_SABD to keep them consistent with other nodes.
---
llvm/docs/GlobalISel/GenericOpcode.rst | 6 +-
.../CodeGen/GlobalISel/MachineIRBuilder.h | 16 +-
llvm/include/llvm/Support/TargetOpcodes.def | 4 +-
llvm/include/llvm/Target/GenericOpcodes.td | 4 +-
.../Target/GlobalISel/SelectionDAGCompat.td | 4 +-
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 26 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 6 +-
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +-
.../GlobalISel/legalizer-info-validation.mir | 6 +-
.../Inputs/reference_x86_vocab_print.txt | 4 +-
.../reference_x86_vocab_wo=0.5_print.txt | 4 +-
.../GlobalISel/legalizer-info-validation.mir | 6 +-
.../legalizer/legalize-abs-diff-rv32.mir | 16 +-
.../legalizer/legalize-abs-diff-rv64.mir | 16 +-
llvm/test/MachineVerifier/test_abd_su.mir | 10 +-
.../output/reference_x86_entities.txt | 434 +++++++++---------
16 files changed, 282 insertions(+), 282 deletions(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 661a11537cf57..1c3d7c80e880b 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -501,15 +501,15 @@ undefined.
%2:_(s33) = G_CTLZ_ZERO_UNDEF %1
%2:_(s33) = G_CTTZ_ZERO_UNDEF %1
-G_ABDS, G_ABDU
+G_SABD, G_UABD
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Compute the absolute difference (signed and unsigned), e.g. trunc(abs(ext(x)-ext(y)).
.. code-block:: none
- %0:_(s33) = G_ABDS %2, %3
- %1:_(s33) = G_ABDU %4, %5
+ %0:_(s33) = G_SABD %2, %3
+ %1:_(s33) = G_UABD %4, %5
Floating Point Operations
-------------------------
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 40c7792f7e8a2..ed10c64d08ad0 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1884,32 +1884,32 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
}
- /// Build and insert \p Res = G_ABDS \p Op0, \p Op1
+ /// Build and insert \p Res = G_SABD \p Op0, \p Op1
///
- /// G_ABDS return the signed absolute difference of \p Op0 and \p Op1.
+ /// G_SABD return the signed absolute difference of \p Op0 and \p Op1.
///
/// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
/// with the same (scalar or vector) type).
///
/// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildAbds(const DstOp &Dst, const SrcOp &Src0,
+ MachineInstrBuilder buildSAbd(const DstOp &Dst, const SrcOp &Src0,
const SrcOp &Src1) {
- return buildInstr(TargetOpcode::G_ABDS, {Dst}, {Src0, Src1});
+ return buildInstr(TargetOpcode::G_SABD, {Dst}, {Src0, Src1});
}
- /// Build and insert \p Res = G_ABDU \p Op0, \p Op1
+ /// Build and insert \p Res = G_UABD \p Op0, \p Op1
///
- /// G_ABDU return the unsigned absolute difference of \p Op0 and \p Op1.
+ /// G_UABD return the unsigned absolute difference of \p Op0 and \p Op1.
///
/// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
/// with the same (scalar or vector) type).
///
/// \return a MachineInstrBuilder for the newly created instruction.
- MachineInstrBuilder buildAbdu(const DstOp &Dst, const SrcOp &Src0,
+ MachineInstrBuilder buildUAbd(const DstOp &Dst, const SrcOp &Src0,
const SrcOp &Src1) {
- return buildInstr(TargetOpcode::G_ABDU, {Dst}, {Src0, Src1});
+ return buildInstr(TargetOpcode::G_UABD, {Dst}, {Src0, Src1});
}
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index e55314568d683..3c307a406c729 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -290,10 +290,10 @@ HANDLE_TARGET_OPCODE(G_OR)
HANDLE_TARGET_OPCODE(G_XOR)
/// Generic absolute difference signed instruction.
-HANDLE_TARGET_OPCODE(G_ABDS)
+HANDLE_TARGET_OPCODE(G_SABD)
/// Generic absolute difference unsigned instruction.
-HANDLE_TARGET_OPCODE(G_ABDU)
+HANDLE_TARGET_OPCODE(G_UABD)
HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index e3f995d53484f..d831af2213dff 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -408,7 +408,7 @@ def G_ASHR : GenericInstruction {
}
// Generic absolute difference signed.
-def G_ABDS : GenericInstruction {
+def G_SABD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = false;
@@ -416,7 +416,7 @@ def G_ABDS : GenericInstruction {
}
// Generic absolute difference unsigned.
-def G_ABDU : GenericInstruction {
+def G_UABD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = false;
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index c0d480294dd8b..dea572bdf11d2 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -81,8 +81,8 @@ def : GINodeEquiv<G_XOR, xor>;
def : GINodeEquiv<G_SHL, shl>;
def : GINodeEquiv<G_LSHR, srl>;
def : GINodeEquiv<G_ASHR, sra>;
-def : GINodeEquiv<G_ABDS, abds>;
-def : GINodeEquiv<G_ABDU, abdu>;
+def : GINodeEquiv<G_SABD, abds>;
+def : GINodeEquiv<G_UABD, abdu>;
def : GINodeEquiv<G_SADDSAT, saddsat>;
def : GINodeEquiv<G_UADDSAT, uaddsat>;
def : GINodeEquiv<G_SSUBSAT, ssubsat>;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 52c43a4ac4a04..ca9adecac361c 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2974,7 +2974,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_SREM:
case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX:
- case TargetOpcode::G_ABDS:
+ case TargetOpcode::G_SABD:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
@@ -3013,7 +3013,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
return Legalized;
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
- case TargetOpcode::G_ABDU:
+ case TargetOpcode::G_UABD:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
@@ -4819,9 +4819,9 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerShlSat(MI);
case G_ABS:
return lowerAbsToAddXor(MI);
- case G_ABDS:
- case G_ABDU: {
- bool IsSigned = MI.getOpcode() == G_ABDS;
+ case G_SABD:
+ case G_UABD: {
+ bool IsSigned = MI.getOpcode() == G_SABD;
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
if ((IsSigned && LI.isLegal({G_SMIN, Ty}) && LI.isLegal({G_SMAX, Ty})) ||
(!IsSigned && LI.isLegal({G_UMIN, Ty}) && LI.isLegal({G_UMAX, Ty}))) {
@@ -10134,9 +10134,9 @@ LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
- assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
- MI.getOpcode() == TargetOpcode::G_ABDU) &&
- "Expected G_ABDS or G_ABDU instruction");
+ assert((MI.getOpcode() == TargetOpcode::G_SABD ||
+ MI.getOpcode() == TargetOpcode::G_UABD) &&
+ "Expected G_SABD or G_UABD instruction");
auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
LLT Ty = MRI.getType(LHS);
@@ -10145,7 +10145,7 @@ LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
// abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
Register LHSSub = MIRBuilder.buildSub(Ty, LHS, RHS).getReg(0);
Register RHSSub = MIRBuilder.buildSub(Ty, RHS, LHS).getReg(0);
- CmpInst::Predicate Pred = (MI.getOpcode() == TargetOpcode::G_ABDS)
+ CmpInst::Predicate Pred = (MI.getOpcode() == TargetOpcode::G_SABD)
? CmpInst::ICMP_SGT
: CmpInst::ICMP_UGT;
auto ICmp = MIRBuilder.buildICmp(Pred, LLT::scalar(1), LHS, RHS);
@@ -10157,9 +10157,9 @@ LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
- assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
- MI.getOpcode() == TargetOpcode::G_ABDU) &&
- "Expected G_ABDS or G_ABDU instruction");
+ assert((MI.getOpcode() == TargetOpcode::G_SABD ||
+ MI.getOpcode() == TargetOpcode::G_UABD) &&
+ "Expected G_SABD or G_UABD instruction");
auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
LLT Ty = MRI.getType(LHS);
@@ -10167,7 +10167,7 @@ LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
// abds(lhs, rhs) -→ sub(smax(lhs, rhs), smin(lhs, rhs))
// abdu(lhs, rhs) -→ sub(umax(lhs, rhs), umin(lhs, rhs))
Register MaxReg, MinReg;
- if (MI.getOpcode() == TargetOpcode::G_ABDS) {
+ if (MI.getOpcode() == TargetOpcode::G_SABD) {
MaxReg = MIRBuilder.buildSMax(Ty, LHS, RHS).getReg(0);
MinReg = MIRBuilder.buildSMin(Ty, LHS, RHS).getReg(0);
} else {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 5f93847bc680e..ac322490d9485 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -289,7 +289,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0)
.lower();
- getActionDefinitionsBuilder({G_ABDS, G_ABDU})
+ getActionDefinitionsBuilder({G_SABD, G_UABD})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lower();
@@ -1814,9 +1814,9 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_umull:
return LowerBinOp(AArch64::G_UMULL);
case Intrinsic::aarch64_neon_sabd:
- return LowerBinOp(TargetOpcode::G_ABDS);
+ return LowerBinOp(TargetOpcode::G_SABD);
case Intrinsic::aarch64_neon_uabd:
- return LowerBinOp(TargetOpcode::G_ABDU);
+ return LowerBinOp(TargetOpcode::G_UABD);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index b1794b78a3e2a..2b4f0e48a7fc4 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -490,7 +490,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();
- getActionDefinitionsBuilder({G_ABDS, G_ABDU})
+ getActionDefinitionsBuilder({G_SABD, G_UABD})
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 896603d6eb20d..3ac868581ed09 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -70,12 +70,12 @@
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
-# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_SABD (opcode [[G_SABD:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
+# DEBUG-NEXT: G_UABD (opcode [[G_UABD:[0-9]+]]): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode [[G_UABD]] is aliased to [[G_SABD]]
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index d3c0da9862245..c4e1f425c9fe3 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -319,8 +319,6 @@ Key: GC_LABEL: [ 0.00 0.00 ]
Key: GETSEC: [ 0.00 0.00 ]
Key: GF: [ 0.00 0.00 ]
Key: GS_PREFIX: [ 0.00 0.00 ]
-Key: G_ABDS: [ 0.00 0.00 ]
-Key: G_ABDU: [ 0.00 0.00 ]
Key: G_ABS: [ 0.00 0.00 ]
Key: G_ADD: [ 0.00 0.00 ]
Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ]
@@ -487,6 +485,7 @@ Key: G_RESET_FPENV: [ 0.00 0.00 ]
Key: G_RESET_FPMODE: [ 0.00 0.00 ]
Key: G_ROTL: [ 0.00 0.00 ]
Key: G_ROTR: [ 0.00 0.00 ]
+Key: G_SABD: [ 0.00 0.00 ]
Key: G_SADDE: [ 0.00 0.00 ]
Key: G_SADDO: [ 0.00 0.00 ]
Key: G_SADDSAT: [ 0.00 0.00 ]
@@ -536,6 +535,7 @@ Key: G_TRUNC: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ]
Key: G_TRUNC_USAT_U: [ 0.00 0.00 ]
+Key: G_UABD: [ 0.00 0.00 ]
Key: G_UADDE: [ 0.00 0.00 ]
Key: G_UADDO: [ 0.00 0.00 ]
Key: G_UADDSAT: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index c6e5508248b9b..a0a55f036fbaf 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -319,8 +319,6 @@ Key: GC_LABEL: [ 0.00 0.00 ]
Key: GETSEC: [ 0.00 0.00 ]
Key: GF: [ 0.00 0.00 ]
Key: GS_PREFIX: [ 0.00 0.00 ]
-Key: G_ABDS: [ 0.00 0.00 ]
-Key: G_ABDU: [ 0.00 0.00 ]
Key: G_ABS: [ 0.00 0.00 ]
Key: G_ADD: [ 0.00 0.00 ]
Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ]
@@ -487,6 +485,7 @@ Key: G_RESET_FPENV: [ 0.00 0.00 ]
Key: G_RESET_FPMODE: [ 0.00 0.00 ]
Key: G_ROTL: [ 0.00 0.00 ]
Key: G_ROTR: [ 0.00 0.00 ]
+Key: G_SABD: [ 0.00 0.00 ]
Key: G_SADDE: [ 0.00 0.00 ]
Key: G_SADDO: [ 0.00 0.00 ]
Key: G_SADDSAT: [ 0.00 0.00 ]
@@ -536,6 +535,7 @@ Key: G_TRUNC: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ]
Key: G_TRUNC_USAT_U: [ 0.00 0.00 ]
+Key: G_UABD: [ 0.00 0.00 ]
Key: G_UADDE: [ 0.00 0.00 ]
Key: G_UADDO: [ 0.00 0.00 ]
Key: G_UADDSAT: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index da7546e12e58b..d69254a9dacda 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -72,12 +72,12 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_SABD (opcode [[G_SABD:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT:G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
+# DEBUG-NEXT:G_UABD (opcode [[G_UABD:[0-9]+]]): 1 type index, 0 imm indices
+# DEBUG-NEXT:.. opcode [[G_UABD]] is aliased to [[G_SABD]]
# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
#
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
index d4a0c3bce6264..f852d790252d1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
@@ -41,7 +41,7 @@ body: |
%4:_(s32) = G_ASSERT_SEXT %2, 8
%5:_(s8) = G_TRUNC %3(s32)
%6:_(s8) = G_TRUNC %4(s32)
- %7:_(s8) = G_ABDS %5, %6
+ %7:_(s8) = G_SABD %5, %6
%8:_(s32) = G_ANYEXT %7(s8)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
@@ -83,7 +83,7 @@ body: |
%4:_(s32) = G_ASSERT_SEXT %2, 16
%5:_(s16) = G_TRUNC %3(s32)
%6:_(s16) = G_TRUNC %4(s32)
- %7:_(s16) = G_ABDS %5, %6
+ %7:_(s16) = G_SABD %5, %6
%8:_(s32) = G_ANYEXT %7(s16)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
@@ -117,7 +117,7 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
- %3:_(s32) = G_ABDS %1, %2
+ %3:_(s32) = G_SABD %1, %2
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
@@ -153,7 +153,7 @@ body: |
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $x11
%5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
- %6:_(s64) = G_ABDS %2, %5
+ %6:_(s64) = G_SABD %2, %5
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$x10 = COPY %7(s32)
$x11 = COPY %8(s32)
@@ -196,7 +196,7 @@ body: |
%4:_(s32) = G_ASSERT_ZEXT %2, 8
%5:_(s8) = G_TRUNC %3(s32)
%6:_(s8) = G_TRUNC %4(s32)
- %7:_(s8) = G_ABDU %5, %6
+ %7:_(s8) = G_UABD %5, %6
%8:_(s32) = G_ANYEXT %7(s8)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
@@ -238,7 +238,7 @@ body: |
%4:_(s32) = G_ASSERT_ZEXT %2, 16
%5:_(s16) = G_TRUNC %3(s32)
%6:_(s16) = G_TRUNC %4(s32)
- %7:_(s16) = G_ABDU %5, %6
+ %7:_(s16) = G_UABD %5, %6
%8:_(s32) = G_ANYEXT %7(s16)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
@@ -272,7 +272,7 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
- %3:_(s32) = G_ABDU %1, %2
+ %3:_(s32) = G_UABD %1, %2
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
@@ -308,7 +308,7 @@ body: |
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $x11
%5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
- %6:_(s64) = G_ABDU %2, %5
+ %6:_(s64) = G_UABD %2, %5
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$x10 = COPY %7(s32)
$x11 = COPY %8(s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir
index deb65d44aa10f..bb8a1edfc951f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir
@@ -44,7 +44,7 @@ body: |
%4:_(s64) = G_ASSERT_SEXT %2, 8
%5:_(s8) = G_TRUNC %3(s64)
%6:_(s8) = G_TRUNC %4(s64)
- %7:_(s8) = G_ABDS %5, %6
+ %7:_(s8) = G_SABD %5, %6
%8:_(s64) = G_ANYEXT %7(s8)
$x10 = COPY %8(s64)
PseudoRET implicit $x10
@@ -90,7 +90,7 @@ body: |
%4:_(s64) = G_ASSERT_SEXT %2, 16
%5:_(s16) = G_TRUNC %3(s64)
%6:_(s16) = G_TRUNC %4(s64)
- %7:_(s16) = G_ABDS %5, %6
+ %7:_(s16) = G_SABD %5, %6
%8:_(s64) = G_ANYEXT %7(s16)
$x10 = COPY %8(s64)
PseudoRET implicit $x10
@@ -138,7 +138,7 @@ body: |
%4:_(s64) = G_ASSERT_SEXT %2, 32
%5:_(s32) = G_TRUNC %3(s64)
%6:_(s32) = G_TRUNC %4(s64)
- %7:_(s32) = G_ABDS %5, %6
+ %7:_(s32) = G_SABD %5, %6
%8:_(s64) = G_ANYEXT %7(s32)
$x10 = COPY %8(s64)
PseudoRET implicit $x10
@@ -168,7 +168,7 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%2:_(s64) = COPY $x11
- %3:_(s64) = G_ABDS %1, %2
+ %3:_(s64) = G_SABD %1, %2
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
@@ -212,7 +212,7 @@ body: |
%4:_(s64) = G_ASSERT_ZEXT %2, 8
%5:_(s8) = G_TRUNC %3(s64)
%6:_(s8) = G_TRUNC %4(s64)
- %7:_(s8) = G_ABDU %5, %6
+ %7:_(s8) = G_UABD %5, %6
%8:_(s64) = G_ANYEXT %7(s8)
$x10 = COPY %8(s64)
PseudoRET implicit $x10
@@ -258,7 +258,7 @@ body: |
%4:_(s64) = G_ASSERT_ZEXT %2, 16
%5:_(s16) = G_TRUNC %3(s64)
%6:_(s16) = G_TRUNC %4(s64)
- %7:_(s16) = G_ABDU %5, %6
+ %7:_(s16) = G_UABD %5, %6
%8:_(s64) = G_ANYEXT %7(s16)
$x10 = COPY %8(s64)
PseudoRET implicit $x10
@@ -308,7 +308,7 @@ body: |
%4:_(s64) = G_ASSERT_ZEXT %2, 32
%5:_(s32) = G_TRUNC %3(s64)
%6:_(s32) = G_TRUNC %4(s64)
- %7:_(s32) = G_ABDU %5, %6
+ %7:_(s32) = G_UABD %5, %6
%8:_(s64) = G_ANYEXT %7(s32)
$x10 = COPY %8(s64)
PseudoRET implicit $x10
@@ -338,7 +338,7 @@ body: |
; RV64ZBB-NEXT: PseudoRET implicit $x10
%1:_(s64) = COPY $x10
%2:_(s64) = COPY $x11
- %3:_(s64) = G_ABDU %1, %2
+ %3:_(s64) = G_UABD %1, %2
$x10 = COPY %3(s64)
PseudoRET implicit $x10
...
diff --git a/llvm/test/MachineVerifier/test_abd_su.mir b/llvm/test/MachineVerifier/test_abd_su.mir
index 992f58c506029..e3561b0223ffd 100644
--- a/llvm/test/MachineVerifier/test_abd_su.mir
+++ b/llvm/test/MachineVerifier/test_abd_su.mir
@@ -10,31 +10,31 @@ body: |
%3:_(p0) = G_IMPLICIT_DEF
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
- %4:_(s1) = G_ABDS %2, %3
+ %4:_(s1) = G_SABD %2, %3
%12:_(s64) = G_IMPLICIT_DEF
%13:_(s64) = G_IMPLICIT_DEF
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
- %14:_(p0) = G_ABDS %12, %13
+ %14:_(p0) = G_SABD %12, %13
%23:_(<2 x s32>) = G_IMPLICIT_DEF
%24:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
- %5:_(s1) = G_ABDU %23, %24
+ %5:_(s1) = G_UABD %23, %24
%15:_(s32) = G_CONSTANT i32 0
%16:_(s64) = G_CONSTANT i64 2
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
- %17:_(s1) = G_ABDU %15, %16
+ %17:_(s1) = G_UABD %15, %16
%18:_(s64) = G_CONSTANT i64 0
%19:_(s64) = G_CONSTANT i64 2
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
- %20:_(s1) = G_ABDU %18, %19
+ %20:_(s1) = G_UABD %18, %19
...
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
index dc436d123fd35..d6de91b30c422 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
@@ -320,223 +320,223 @@ GC_LABEL 317
GETSEC 318
GF 319
GS_PREFIX 320
-G_ABDS 321
-G_ABDU 322
-G_ABS 323
-G_ADD 324
-G_ADDRSPACE_CAST 325
-G_AND 326
-G_ANYEXT 327
-G_ASHR 328
-G_ASSERT_ALIGN 329
-G_ASSERT_SEXT 330
-G_ASSERT_ZEXT 331
-G_ATOMICRMW_ADD 332
-G_ATOMICRMW_AND 333
-G_ATOMICRMW_FADD 334
-G_ATOMICRMW_FMAX 335
-G_ATOMICRMW_FMAXIMUM 336
-G_ATOMICRMW_FMIN 337
-G_ATOMICRMW_FMINIMUM 338
-G_ATOMICRMW_FSUB 339
-G_ATOMICRMW_MAX 340
-G_ATOMICRMW_MIN 341
-G_ATOMICRMW_NAND 342
-G_ATOMICRMW_OR 343
-G_ATOMICRMW_SUB 344
-G_ATOMICRMW_UDEC_WRAP 345
-G_ATOMICRMW_UINC_WRAP 346
-G_ATOMICRMW_UMAX 347
-G_ATOMICRMW_UMIN 348
-G_ATOMICRMW_USUB_COND 349
-G_ATOMICRMW_USUB_SAT 350
-G_ATOMICRMW_XCHG 351
-G_ATOMICRMW_XOR 352
-G_ATOMIC_CMPXCHG 353
-G_ATOMIC_CMPXCHG_WITH_SUCCESS 354
-G_BITCAST 355
-G_BITREVERSE 356
-G_BLOCK_ADDR 357
-G_BR 358
-G_BRCOND 359
-G_BRINDIRECT 360
-G_BRJT 361
-G_BSWAP 362
-G_BUILD_VECTOR 363
-G_BUILD_VECTOR_TRUNC 364
-G_BZERO 365
-G_CONCAT_VECTORS 366
-G_CONSTANT 367
-G_CONSTANT_FOLD_BARRIER 368
-G_CONSTANT_POOL 369
-G_CTLZ 370
-G_CTLZ_ZERO_UNDEF 371
-G_CTPOP 372
-G_CTTZ 373
-G_CTTZ_ZERO_UNDEF 374
-G_DEBUGTRAP 375
-G_DYN_STACKALLOC 376
-G_EXTRACT 377
-G_EXTRACT_SUBVECTOR 378
-G_EXTRACT_VECTOR_ELT 379
-G_FABS 380
-G_FACOS 381
-G_FADD 382
-G_FASIN 383
-G_FATAN 384
-G_FCANONICALIZE 385
-G_FCEIL 386
-G_FCMP 387
-G_FCONSTANT 388
-G_FCOPYSIGN 389
-G_FCOS 390
-G_FCOSH 391
-G_FDIV 392
-G_FENCE 393
-G_FEXP 394
-G_FFLOOR 395
-G_FFREXP 396
-G_FILD 397
-G_FIST 398
-G_FLDCW 399
-G_FLDEXP 400
-G_FLOG 401
-G_FMA 402
-G_FMAD 403
-G_FMAXIMUM 404
-G_FMAXIMUMNUM 405
-G_FMAXNUM 406
-G_FMAXNUM_IEEE 407
-G_FMINIMUM 408
-G_FMINIMUMNUM 409
-G_FMINNUM 410
-G_FMINNUM_IEEE 411
-G_FMODF 412
-G_FMUL 413
-G_FNEARBYINT 414
-G_FNEG 415
-G_FNSTCW 416
-G_FPEXT 417
-G_FPOW 418
-G_FPOWI 419
-G_FPTOSI 420
-G_FPTOSI_SAT 421
-G_FPTOUI 422
-G_FPTOUI_SAT 423
-G_FPTRUNC 424
-G_FRAME_INDEX 425
-G_FREEZE 426
-G_FREM 427
-G_FRINT 428
-G_FSHL 429
-G_FSHR 430
-G_FSIN 431
-G_FSINCOS 432
-G_FSINH 433
-G_FSQRT 434
-G_FSUB 435
-G_FTAN 436
-G_FTANH 437
-G_GET_FPENV 438
-G_GET_FPMODE 439
-G_GET_ROUNDING 440
-G_GLOBAL_VALUE 441
-G_ICMP 442
-G_IMPLICIT_DEF 443
-G_INDEXED_LOAD 444
-G_INDEXED_SEXTLOAD 445
-G_INDEXED_STORE 446
-G_INDEXED_ZEXTLOAD 447
-G_INSERT 448
-G_INSERT_SUBVECTOR 449
-G_INSERT_VECTOR_ELT 450
-G_INTRINSIC 451
-G_INTRINSIC_CONVERGENT 452
-G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 453
-G_INTRINSIC_FPTRUNC_ROUND 454
-G_INTRINSIC_LLRINT 455
-G_INTRINSIC_LRINT 456
-G_INTRINSIC_ROUND 457
-G_INTRINSIC_ROUNDEVEN 458
-G_INTRINSIC_TRUNC 459
-G_INTRINSIC_W_SIDE_EFFECTS 460
-G_INTTOPTR 461
-G_INVOKE_REGION_START 462
-G_IS_FPCLASS 463
-G_JUMP_TABLE 464
-G_LLROUND 465
-G_LOAD 466
-G_LROUND 467
-G_LSHR 468
-G_MEMCPY 469
-G_MEMCPY_INLINE 470
-G_MEMMOVE 471
-G_MEMSET 472
-G_MERGE_VALUES 473
-G_MUL 474
-G_OR 475
-G_PHI 476
-G_PREFETCH 477
-G_PTRAUTH_GLOBAL_VALUE 478
-G_PTRMASK 479
-G_PTRTOINT 480
-G_PTR_ADD 481
-G_READCYCLECOUNTER 482
-G_READSTEADYCOUNTER 483
-G_READ_REGISTER 484
-G_RESET_FPENV 485
-G_RESET_FPMODE 486
-G_ROTL 487
-G_ROTR 488
-G_SADDE 489
-G_SADDO 490
-G_SADDSAT 491
-G_SBFX 492
-G_SCMP 493
-G_SDIV 494
-G_SDIVFIX 495
-G_SDIVFIXSAT 496
-G_SDIVREM 497
-G_SELECT 498
-G_SET_FPENV 499
-G_SET_FPMODE 500
-G_SET_ROUNDING 501
-G_SEXT 502
-G_SEXTLOAD 503
-G_SEXT_INREG 504
-G_SHL 505
-G_SHUFFLE_VECTOR 506
-G_SITOFP 507
-G_SMAX 508
-G_SMIN 509
-G_SMULFIX 510
-G_SMULFIXSAT 511
-G_SMULH 512
-G_SMULO 513
-G_SPLAT_VECTOR 514
-G_SREM 515
-G_SSHLSAT 516
-G_SSUBE 517
-G_SSUBO 518
-G_SSUBSAT 519
-G_STACKRESTORE 520
-G_STACKSAVE 521
-G_STEP_VECTOR 522
-G_STORE 523
-G_STRICT_FADD 524
-G_STRICT_FDIV 525
-G_STRICT_FLDEXP 526
-G_STRICT_FMA 527
-G_STRICT_FMUL 528
-G_STRICT_FREM 529
-G_STRICT_FSQRT 530
-G_STRICT_FSUB 531
-G_SUB 532
-G_TRAP 533
-G_TRUNC 534
-G_TRUNC_SSAT_S 535
-G_TRUNC_SSAT_U 536
-G_TRUNC_USAT_U 537
+G_ABS 321
+G_ADD 322
+G_ADDRSPACE_CAST 323
+G_AND 324
+G_ANYEXT 325
+G_ASHR 326
+G_ASSERT_ALIGN 327
+G_ASSERT_SEXT 328
+G_ASSERT_ZEXT 329
+G_ATOMICRMW_ADD 330
+G_ATOMICRMW_AND 331
+G_ATOMICRMW_FADD 332
+G_ATOMICRMW_FMAX 333
+G_ATOMICRMW_FMAXIMUM 334
+G_ATOMICRMW_FMIN 335
+G_ATOMICRMW_FMINIMUM 336
+G_ATOMICRMW_FSUB 337
+G_ATOMICRMW_MAX 338
+G_ATOMICRMW_MIN 339
+G_ATOMICRMW_NAND 340
+G_ATOMICRMW_OR 341
+G_ATOMICRMW_SUB 342
+G_ATOMICRMW_UDEC_WRAP 343
+G_ATOMICRMW_UINC_WRAP 344
+G_ATOMICRMW_UMAX 345
+G_ATOMICRMW_UMIN 346
+G_ATOMICRMW_USUB_COND 347
+G_ATOMICRMW_USUB_SAT 348
+G_ATOMICRMW_XCHG 349
+G_ATOMICRMW_XOR 350
+G_ATOMIC_CMPXCHG 351
+G_ATOMIC_CMPXCHG_WITH_SUCCESS 352
+G_BITCAST 353
+G_BITREVERSE 354
+G_BLOCK_ADDR 355
+G_BR 356
+G_BRCOND 357
+G_BRINDIRECT 358
+G_BRJT 359
+G_BSWAP 360
+G_BUILD_VECTOR 361
+G_BUILD_VECTOR_TRUNC 362
+G_BZERO 363
+G_CONCAT_VECTORS 364
+G_CONSTANT 365
+G_CONSTANT_FOLD_BARRIER 366
+G_CONSTANT_POOL 367
+G_CTLZ 368
+G_CTLZ_ZERO_UNDEF 369
+G_CTPOP 370
+G_CTTZ 371
+G_CTTZ_ZERO_UNDEF 372
+G_DEBUGTRAP 373
+G_DYN_STACKALLOC 374
+G_EXTRACT 375
+G_EXTRACT_SUBVECTOR 376
+G_EXTRACT_VECTOR_ELT 377
+G_FABS 378
+G_FACOS 379
+G_FADD 380
+G_FASIN 381
+G_FATAN 382
+G_FCANONICALIZE 383
+G_FCEIL 384
+G_FCMP 385
+G_FCONSTANT 386
+G_FCOPYSIGN 387
+G_FCOS 388
+G_FCOSH 389
+G_FDIV 390
+G_FENCE 391
+G_FEXP 392
+G_FFLOOR 393
+G_FFREXP 394
+G_FILD 395
+G_FIST 396
+G_FLDCW 397
+G_FLDEXP 398
+G_FLOG 399
+G_FMA 400
+G_FMAD 401
+G_FMAXIMUM 402
+G_FMAXIMUMNUM 403
+G_FMAXNUM 404
+G_FMAXNUM_IEEE 405
+G_FMINIMUM 406
+G_FMINIMUMNUM 407
+G_FMINNUM 408
+G_FMINNUM_IEEE 409
+G_FMODF 410
+G_FMUL 411
+G_FNEARBYINT 412
+G_FNEG 413
+G_FNSTCW 414
+G_FPEXT 415
+G_FPOW 416
+G_FPOWI 417
+G_FPTOSI 418
+G_FPTOSI_SAT 419
+G_FPTOUI 420
+G_FPTOUI_SAT 421
+G_FPTRUNC 422
+G_FRAME_INDEX 423
+G_FREEZE 424
+G_FREM 425
+G_FRINT 426
+G_FSHL 427
+G_FSHR 428
+G_FSIN 429
+G_FSINCOS 430
+G_FSINH 431
+G_FSQRT 432
+G_FSUB 433
+G_FTAN 434
+G_FTANH 435
+G_GET_FPENV 436
+G_GET_FPMODE 437
+G_GET_ROUNDING 438
+G_GLOBAL_VALUE 439
+G_ICMP 440
+G_IMPLICIT_DEF 441
+G_INDEXED_LOAD 442
+G_INDEXED_SEXTLOAD 443
+G_INDEXED_STORE 444
+G_INDEXED_ZEXTLOAD 445
+G_INSERT 446
+G_INSERT_SUBVECTOR 447
+G_INSERT_VECTOR_ELT 448
+G_INTRINSIC 449
+G_INTRINSIC_CONVERGENT 450
+G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 451
+G_INTRINSIC_FPTRUNC_ROUND 452
+G_INTRINSIC_LLRINT 453
+G_INTRINSIC_LRINT 454
+G_INTRINSIC_ROUND 455
+G_INTRINSIC_ROUNDEVEN 456
+G_INTRINSIC_TRUNC 457
+G_INTRINSIC_W_SIDE_EFFECTS 458
+G_INTTOPTR 459
+G_INVOKE_REGION_START 460
+G_IS_FPCLASS 461
+G_JUMP_TABLE 462
+G_LLROUND 463
+G_LOAD 464
+G_LROUND 465
+G_LSHR 466
+G_MEMCPY 467
+G_MEMCPY_INLINE 468
+G_MEMMOVE 469
+G_MEMSET 470
+G_MERGE_VALUES 471
+G_MUL 472
+G_OR 473
+G_PHI 474
+G_PREFETCH 475
+G_PTRAUTH_GLOBAL_VALUE 476
+G_PTRMASK 477
+G_PTRTOINT 478
+G_PTR_ADD 479
+G_READCYCLECOUNTER 480
+G_READSTEADYCOUNTER 481
+G_READ_REGISTER 482
+G_RESET_FPENV 483
+G_RESET_FPMODE 484
+G_ROTL 485
+G_ROTR 486
+G_SABD 487
+G_SADDE 488
+G_SADDO 489
+G_SADDSAT 490
+G_SBFX 491
+G_SCMP 492
+G_SDIV 493
+G_SDIVFIX 494
+G_SDIVFIXSAT 495
+G_SDIVREM 496
+G_SELECT 497
+G_SET_FPENV 498
+G_SET_FPMODE 499
+G_SET_ROUNDING 500
+G_SEXT 501
+G_SEXTLOAD 502
+G_SEXT_INREG 503
+G_SHL 504
+G_SHUFFLE_VECTOR 505
+G_SITOFP 506
+G_SMAX 507
+G_SMIN 508
+G_SMULFIX 509
+G_SMULFIXSAT 510
+G_SMULH 511
+G_SMULO 512
+G_SPLAT_VECTOR 513
+G_SREM 514
+G_SSHLSAT 515
+G_SSUBE 516
+G_SSUBO 517
+G_SSUBSAT 518
+G_STACKRESTORE 519
+G_STACKSAVE 520
+G_STEP_VECTOR 521
+G_STORE 522
+G_STRICT_FADD 523
+G_STRICT_FDIV 524
+G_STRICT_FLDEXP 525
+G_STRICT_FMA 526
+G_STRICT_FMUL 527
+G_STRICT_FREM 528
+G_STRICT_FSQRT 529
+G_STRICT_FSUB 530
+G_SUB 531
+G_TRAP 532
+G_TRUNC 533
+G_TRUNC_SSAT_S 534
+G_TRUNC_SSAT_U 535
+G_TRUNC_USAT_U 536
+G_UABD 537
G_UADDE 538
G_UADDO 539
G_UADDSAT 540
More information about the llvm-commits
mailing list