[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Brandon Wu via llvm-commits]

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@@ -14561,6 +14671,19 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       return;
     }
 
+    if (Subtarget.hasStdExtP() && Subtarget.is64Bit()) {
+      SDLoc DL(N);
+      SDValue ExtLoad =
+          DAG.getExtLoad(ISD::SEXTLOAD, DL, MVT::i64, Ld->getChain(),
+                         Ld->getBasePtr(), MVT::i32, Ld->getMemOperand());
+      if (N->getValueType(0) == MVT::v2i16)
+        Results.push_back(DAG.getBitcast(MVT::v4i16, ExtLoad));
+      else if (N->getValueType(0) == MVT::v4i8)
+        Results.push_back(DAG.getBitcast(MVT::v8i8, ExtLoad));
+      Results.push_back(ExtLoad.getValue(1));
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4vtomat wrote:

Uh I see, nice catch!

https://github.com/llvm/llvm-project/pull/162668