[llvm] [Instcombine] Avoid widening trunc+sext to trunc+shl+ashr when not profitable (PR #160483)

[Wenju He via llvm-commits]

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@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+target datalayout = "i16:16:16-i32:32:32-i64:64:64-n16:32:64"
+
+define i32 @test(i64 %i) {
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wenju-he wrote:

> Can you please add a test with `trunc nsw`?
> 
> ```
> define i32 @test(i64 %i) {
>   %a = trunc nsw i64 %i to i16
>   %b = sext i16 %a to i32
>   ret i32 %b
> }
> ```
> 
> It should be folded into `trunc nsw i64 %i to i32`.

Thanks for the suggestion. Done in https://github.com/llvm/llvm-project/pull/160483/commits/1c5d59941cb6a757e0fc7a88b5338da21d7bf0f1. It requires an additional change to the part `If the input has more sign bits than bits truncated, then convert directly to final type`. Please review.

https://github.com/llvm/llvm-project/pull/160483