[llvm] [Xtensa] Fix S32C1I instruction encoding and copyPhysReg. (PR #165174)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
index d1c4d68df..30976be3f 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -132,7 +132,7 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
            Xtensa::FPRRegClass.contains(DestReg))
     Opcode = Xtensa::WFR;
   else
-     report_fatal_error("Impossible reg-to-reg copy");
+    report_fatal_error("Impossible reg-to-reg copy");
 
   BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc));

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https://github.com/llvm/llvm-project/pull/165174