[llvm] [ARM] Only change mask if demanded bits says we can optimize (PR #165106)
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Sat Oct 25 17:33:34 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/165106
>From e9be61c1c74615177cfb55b9205e253b4a539059 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 25 Oct 2025 12:27:59 -0400
Subject: [PATCH 1/2] [ARM] Only change mask if demanded bits says we can
optimize
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 34 ++++++++++++++++++++-----
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 313ae3d68fb83..d8bc59177722e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20138,6 +20138,17 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
}
}
+static bool isLegalLogicalImmediate(unsigned Imm,
+ const ARMSubtarget *Subtarget) {
+ // Handle special cases first
+ if (!Subtarget->isThumb())
+ return ARM_AM::getSOImmVal(Imm) != -1;
+ if (Subtarget->isThumb2())
+ return ARM_AM::getT2SOImmVal(Imm) != -1;
+ // Thumb1 only has 8-bit unsigned immediate.
+ return Imm <= 255;
+}
+
bool ARMTargetLowering::targetShrinkDemandedConstant(
SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
TargetLoweringOpt &TLO) const {
@@ -20180,6 +20191,14 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
if (ExpandedMask == ~0U)
return TLO.CombineTo(Op, Op.getOperand(0));
+ // Don't optimize if it is legal already.
+ if (isLegalLogicalImmediate(Mask, Subtarget))
+ return false;
+
+ // bic
+ if (isLegalLogicalImmediate(~Mask, Subtarget))
+ return false;
+
auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;
};
@@ -20200,14 +20219,16 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
if (IsLegalMask(0xFFFF))
return UseMask(0xFFFF);
- // [1, 255] is Thumb1 movs+ands, legal immediate for ARM/Thumb2.
- // FIXME: Prefer a contiguous sequence of bits for other optimizations.
- if (ShrunkMask < 256)
+ if (isLegalLogicalImmediate(ShrunkMask, Subtarget))
return UseMask(ShrunkMask);
- // [-256, -2] is Thumb1 movs+bics, legal immediate for ARM/Thumb2.
- // FIXME: Prefer a contiguous sequence of bits for other optimizations.
- if ((int)ExpandedMask <= -2 && (int)ExpandedMask >= -256)
+ if (isLegalLogicalImmediate(~ShrunkMask, Subtarget))
+ return UseMask(ShrunkMask);
+
+ if (isLegalLogicalImmediate(ExpandedMask, Subtarget))
+ return UseMask(ExpandedMask);
+
+ if (isLegalLogicalImmediate(~ExpandedMask, Subtarget))
return UseMask(ExpandedMask);
// Potential improvements:
@@ -20215,7 +20236,6 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
// We could try to recognize lsls+lsrs or lsrs+lsls pairs here.
// We could try to prefer Thumb1 immediates which can be lowered to a
// two-instruction sequence.
- // We could try to recognize more legal ARM/Thumb2 immediates here.
return false;
}
>From defe297aae6d90a1e02c0f97f4e3dc85ede57eb4 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 25 Oct 2025 20:33:23 -0400
Subject: [PATCH 2/2] Update ARMISelLowering.cpp
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 ------
1 file changed, 6 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d8bc59177722e..9bbd3f7b736f3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20222,12 +20222,6 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
if (isLegalLogicalImmediate(ShrunkMask, Subtarget))
return UseMask(ShrunkMask);
- if (isLegalLogicalImmediate(~ShrunkMask, Subtarget))
- return UseMask(ShrunkMask);
-
- if (isLegalLogicalImmediate(ExpandedMask, Subtarget))
- return UseMask(ExpandedMask);
-
if (isLegalLogicalImmediate(~ExpandedMask, Subtarget))
return UseMask(ExpandedMask);
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