[llvm] Remove Manual combine-to (PR #165106)

[via llvm-commits]

https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/165106

>From dbff538b01bcc4b35b2c6acdb40d5147c76f2b2c Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 25 Oct 2025 12:27:59 -0400
Subject: [PATCH 1/2] Remove Manual combine-to

---
 llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 313ae3d68fb83..9b7955eda8f8d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20178,7 +20178,7 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
   // code won't do this, so we have to do it explicitly to avoid an infinite
   // loop in obscure cases.)
   if (ExpandedMask == ~0U)
-    return TLO.CombineTo(Op, Op.getOperand(0));
+    return false;
 
   auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
     return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;

>From c57e5348da79100700da88f50383d2c73b5d956c Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 25 Oct 2025 18:25:20 -0400
Subject: [PATCH 2/2] Do not change demanded bits if it is already legal

---
 llvm/lib/Target/ARM/ARMISelLowering.cpp | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9b7955eda8f8d..daaba542e731f 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20138,6 +20138,16 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   }
 }
 
+static bool isLegalLogicalImmediate(unsigned Imm, const ARMSubtarget *Subtarget) {
+  // Handle special cases first
+  if (!Subtarget->isThumb())
+    return ARM_AM::getSOImmVal(Imm) != -1;
+  if (Subtarget->isThumb2())
+    return ARM_AM::getT2SOImmVal(Imm) != -1;
+  // Thumb1 only has 8-bit unsigned immediate.
+  return Imm <= 255;
+}
+
 bool ARMTargetLowering::targetShrinkDemandedConstant(
     SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
     TargetLoweringOpt &TLO) const {
@@ -20178,6 +20188,14 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
   // code won't do this, so we have to do it explicitly to avoid an infinite
   // loop in obscure cases.)
   if (ExpandedMask == ~0U)
+    return TLO.CombineTo(Op, Op.getOperand(0));
+
+  // Don't optimize if it is legal already.
+  if (isLegalLogicalImmediate(Mask, Subtarget))
+    return false;
+
+  // bic
+  if (isLegalLogicalImmediate(~Mask, Subtarget))
     return false;
 
   auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
@@ -20215,7 +20233,6 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
   // We could try to recognize lsls+lsrs or lsrs+lsls pairs here.
   // We could try to prefer Thumb1 immediates which can be lowered to a
   // two-instruction sequence.
-  // We could try to recognize more legal ARM/Thumb2 immediates here.
 
   return false;
 }