[llvm] [RISCV] 'Zalrsc' may permit non-base instructions (PR #165042)

[via llvm-commits]

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@@ -1906,6 +1906,22 @@ def FeatureForcedAtomics : SubtargetFeature<
 def HasAtomicLdSt
     : Predicate<"Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">;
 
+// The RISC-V Unprivileged Architecture defines _constrained_ LR/SC loops:
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slachowsky wrote:

Done

https://github.com/llvm/llvm-project/pull/165042