[llvm] [RISCV] 'Zalrsc' may permit non-base instructions (PR #165042)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 24 16:06:50 PDT 2025
================
@@ -0,0 +1,1074 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32I-ZALRSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+b,+zalrsc,+permissive-zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32IB-ZALRSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV32IA %s
+;
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64I-ZALRSC %s
+; RUN: llc -mtriple=riscv64 -mattr=+b,+zalrsc,+permissive-zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IB-ZALRSC %s
+; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA %s
+
+define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; RV32I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a3, a1, .LBB0_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB0_3: # in Loop: Header=BB0_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB0_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
+; RV32IB-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
+; RV32IB-ZALRSC: # %bb.0:
+; RV32IB-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV32IB-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32IB-ZALRSC-NEXT: max a3, a2, a1
+; RV32IB-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32IB-ZALRSC-NEXT: bnez a3, .LBB0_1
+; RV32IB-ZALRSC-NEXT: # %bb.2:
+; RV32IB-ZALRSC-NEXT: mv a0, a2
+; RV32IB-ZALRSC-NEXT: ret
+;
+; RV32IA-LABEL: atomicrmw_max_i32_seq_cst:
+; RV32IA: # %bb.0:
+; RV32IA-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV32IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
+; RV64I-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB0_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB0_3: # in Loop: Header=BB0_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB0_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
+;
+; RV64IB-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64IB-ZALRSC: # %bb.0:
+; RV64IB-ZALRSC-NEXT: sext.w a2, a1
+; RV64IB-ZALRSC-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IB-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64IB-ZALRSC-NEXT: max a3, a1, a2
+; RV64IB-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IB-ZALRSC-NEXT: bnez a3, .LBB0_1
+; RV64IB-ZALRSC-NEXT: # %bb.2:
+; RV64IB-ZALRSC-NEXT: mv a0, a1
+; RV64IB-ZALRSC-NEXT: ret
+;
+; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT: ret
+ %1 = atomicrmw max ptr %a, i32 %b seq_cst
+ ret i32 %1
+}
+
+define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; RV32I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bge a1, a3, .LBB1_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB1_3: # in Loop: Header=BB1_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB1_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
+; RV32IB-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
+; RV32IB-ZALRSC: # %bb.0:
+; RV32IB-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV32IB-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32IB-ZALRSC-NEXT: min a3, a2, a1
+; RV32IB-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32IB-ZALRSC-NEXT: bnez a3, .LBB1_1
+; RV32IB-ZALRSC-NEXT: # %bb.2:
+; RV32IB-ZALRSC-NEXT: mv a0, a2
+; RV32IB-ZALRSC-NEXT: ret
+;
+; RV32IA-LABEL: atomicrmw_min_i32_seq_cst:
+; RV32IA: # %bb.0:
+; RV32IA-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV32IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
+; RV64I-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB1_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB1_3: # in Loop: Header=BB1_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB1_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
+;
+; RV64IB-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64IB-ZALRSC: # %bb.0:
+; RV64IB-ZALRSC-NEXT: sext.w a2, a1
+; RV64IB-ZALRSC-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IB-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64IB-ZALRSC-NEXT: min a3, a1, a2
+; RV64IB-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IB-ZALRSC-NEXT: bnez a3, .LBB1_1
+; RV64IB-ZALRSC-NEXT: # %bb.2:
+; RV64IB-ZALRSC-NEXT: mv a0, a1
+; RV64IB-ZALRSC-NEXT: ret
+;
+; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT: ret
+ %1 = atomicrmw min ptr %a, i32 %b seq_cst
+ ret i32 %1
+}
+
+define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; RV32I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV32I-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32I-ZALRSC-NEXT: mv a3, a2
+; RV32I-ZALRSC-NEXT: bgeu a3, a1, .LBB2_3
+; RV32I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV32I-ZALRSC-NEXT: mv a3, a1
+; RV32I-ZALRSC-NEXT: .LBB2_3: # in Loop: Header=BB2_1 Depth=1
+; RV32I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32I-ZALRSC-NEXT: bnez a3, .LBB2_1
+; RV32I-ZALRSC-NEXT: # %bb.4:
+; RV32I-ZALRSC-NEXT: mv a0, a2
+; RV32I-ZALRSC-NEXT: ret
+;
+; RV32IB-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV32IB-ZALRSC: # %bb.0:
+; RV32IB-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV32IB-ZALRSC-NEXT: lr.w.aqrl a2, (a0)
+; RV32IB-ZALRSC-NEXT: maxu a3, a2, a1
+; RV32IB-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV32IB-ZALRSC-NEXT: bnez a3, .LBB2_1
+; RV32IB-ZALRSC-NEXT: # %bb.2:
+; RV32IB-ZALRSC-NEXT: mv a0, a2
+; RV32IB-ZALRSC-NEXT: ret
+;
+; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV32IA: # %bb.0:
+; RV32IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV32IA-NEXT: ret
+;
+; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sext.w a2, a1
+; RV64I-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64I-ZALRSC-NEXT: mv a3, a1
+; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB2_3
+; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV64I-ZALRSC-NEXT: mv a3, a2
+; RV64I-ZALRSC-NEXT: .LBB2_3: # in Loop: Header=BB2_1 Depth=1
+; RV64I-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64I-ZALRSC-NEXT: bnez a3, .LBB2_1
+; RV64I-ZALRSC-NEXT: # %bb.4:
+; RV64I-ZALRSC-NEXT: mv a0, a1
+; RV64I-ZALRSC-NEXT: ret
+;
+; RV64IB-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64IB-ZALRSC: # %bb.0:
+; RV64IB-ZALRSC-NEXT: sext.w a2, a1
+; RV64IB-ZALRSC-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IB-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
+; RV64IB-ZALRSC-NEXT: maxu a3, a1, a2
+; RV64IB-ZALRSC-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IB-ZALRSC-NEXT: bnez a3, .LBB2_1
+; RV64IB-ZALRSC-NEXT: # %bb.2:
+; RV64IB-ZALRSC-NEXT: mv a0, a1
+; RV64IB-ZALRSC-NEXT: ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT: ret
+ %1 = atomicrmw umax ptr %a, i32 %b seq_cst
----------------
slachowsky wrote:
An ordering was required, it is not relevant which was chosen. This ordering modes are tested extensively in other tests.
https://github.com/llvm/llvm-project/pull/165042
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