[llvm] [RISCV] 'Zalrsc' may permit non-base instructions (PR #165042)

[via llvm-commits]

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@@ -0,0 +1,1074 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV32I-ZALRSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+b,+zalrsc,+permissive-zalrsc -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV32IB-ZALRSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV32IA %s
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slachowsky wrote:

The `+a` feature is already tested elsewhere.  This is a focused test specifically on the possible lowering paths for 32/64-bit min/max atomics, meant to show the progressively improved sequence for `+permissive-zalrsc` and that it does not tamper with `+a`.

https://github.com/llvm/llvm-project/pull/165042