[llvm] [RISCV] 'Zalrsc' may permit non-base instructions (PR #165042)

Francesco Petrogalli via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 24 15:54:20 PDT 2025


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@@ -1906,6 +1906,22 @@ def FeatureForcedAtomics : SubtargetFeature<
 def HasAtomicLdSt
     : Predicate<"Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">;
 
+// The RISC-V Unprivileged Architecture defines _constrained_ LR/SC loops:
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fpetrogalli wrote:

nit: link to the specs, and reference to section

https://github.com/llvm/llvm-project/pull/165042


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