[llvm] [RISCV] 'Zalrsc' may permit non-base instructions (PR #165042)

[Francesco Petrogalli via llvm-commits]

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@@ -682,6 +702,9 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
     MachineBasicBlock::iterator &NextMBBI) {
+  // Using MIN(U)/MAX(U) is preferrable if permitted
+  if (STI->hasPermissiveZalrsc() && STI->hasStdExtZbb() && !IsMasked)
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fpetrogalli wrote:

given that `hasPermissiveZalrsc` is not implying `Zalrsc`, I would add an assert here that say `hasStdExtZalrsc`.

https://github.com/llvm/llvm-project/pull/165042