[llvm] [X86] Remove LOW32_ADDR_ACCESS_RBP RegisterClass (PR #165018)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 24 12:39:47 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlgo
Author: None (jiang1997)
<details>
<summary>Changes</summary>
This removes the LOW32_ADDR_ACCESS_RBP RegisterClass and refreshes all affected codegen tests
Fixes #<!-- -->155430
---
Patch is 215.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/165018.diff
51 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86RegisterInfo.td (-4)
- (modified) llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir (+4-4)
- (modified) llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt (-14)
- (modified) llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt (-14)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-copy.mir (+68-64)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-ext.mir (+103-38)
- (modified) llvm/test/CodeGen/X86/abds-neg.ll (+39-40)
- (modified) llvm/test/CodeGen/X86/abds.ll (+30-24)
- (modified) llvm/test/CodeGen/X86/abdu-neg.ll (+39-40)
- (modified) llvm/test/CodeGen/X86/abdu.ll (+75-60)
- (modified) llvm/test/CodeGen/X86/abs.ll (+21-18)
- (modified) llvm/test/CodeGen/X86/asm-mismatched-types.ll (+44-44)
- (modified) llvm/test/CodeGen/X86/asm-reject-rex.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/bitselect.ll (+26-23)
- (modified) llvm/test/CodeGen/X86/byval2.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/byval3.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/byval4.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll (+5-5)
- (modified) llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll (+30-28)
- (modified) llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll (+15-13)
- (modified) llvm/test/CodeGen/X86/fshl.ll (+67-69)
- (modified) llvm/test/CodeGen/X86/fshr.ll (+23-23)
- (modified) llvm/test/CodeGen/X86/funnel-shift.ll (+11-11)
- (modified) llvm/test/CodeGen/X86/i128-sdiv.ll (+331-21)
- (modified) llvm/test/CodeGen/X86/iabs.ll (+21-18)
- (modified) llvm/test/CodeGen/X86/peephole-copy.mir (+4-4)
- (modified) llvm/test/CodeGen/X86/physreg-pairs-error.ll (+4-3)
- (modified) llvm/test/CodeGen/X86/physreg-pairs.ll (+11-11)
- (modified) llvm/test/CodeGen/X86/popcnt.ll (+197-192)
- (modified) llvm/test/CodeGen/X86/pr34080-2.ll (+5-5)
- (modified) llvm/test/CodeGen/X86/pr86880.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/regallocfast-callbr-asm-spills-after-reload.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/scheduler-asm-moves.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/scmp.ll (+17-17)
- (modified) llvm/test/CodeGen/X86/sdiv_fix.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/sdiv_fix_sat.ll (+17-16)
- (modified) llvm/test/CodeGen/X86/shift-i128.ll (+179-177)
- (modified) llvm/test/CodeGen/X86/shift-i256.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/smax.ll (+16-13)
- (modified) llvm/test/CodeGen/X86/smin.ll (+29-26)
- (modified) llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/ucmp.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/umax.ll (+16-13)
- (modified) llvm/test/CodeGen/X86/umin.ll (+29-26)
- (modified) llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll (+10-8)
- (modified) llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt (+22-22)
- (modified) llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt (+228-242)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 410f20edc6281..c2e079448d24d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61664,8 +61664,7 @@ static bool isGRClass(const TargetRegisterClass &RC) {
return RC.hasSuperClassEq(&X86::GR8RegClass) ||
RC.hasSuperClassEq(&X86::GR16RegClass) ||
RC.hasSuperClassEq(&X86::GR32RegClass) ||
- RC.hasSuperClassEq(&X86::GR64RegClass) ||
- RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass);
+ RC.hasSuperClassEq(&X86::GR64RegClass);
}
/// Check if \p RC is a vector register class.
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 99b7910131dc5..1c58b31700b75 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -716,10 +716,6 @@ def GR64_NOREX2_NOSP : RegisterClass<"X86", [i64], 64,
// which we do not have right now.
def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;
-// FIXME: This is unused, but deleting it results in codegen changes
-def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
- (add LOW32_ADDR_ACCESS, RBP)>;
-
// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
diff --git a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
index 54145a4224895..0ccf7014b8e55 100644
--- a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
@@ -28,8 +28,8 @@ body: |
liveins: $rdi, $rsi
; CHECK-LABEL: name: test
- ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4784138 /* regdef:GR64 */, def $rsi, 4784138 /* regdef:GR64 */, def dead $rdi,
- INLINEASM &foo, 0, 4784138, def $rsi, 4784138, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
+ ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4390922 /* regdef:GR64 */, def $rsi, 4390922 /* regdef:GR64 */, def dead $rdi,
+ INLINEASM &foo, 0, 4390922, def $rsi, 4390922, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
$rax = MOV64rr killed $rsi
RET64 killed $rax
...
@@ -45,8 +45,8 @@ body: |
; Verify that the register ties are preserved.
; CHECK-LABEL: name: test2
- ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4784138 /* regdef:GR64 */, def $rsi, 4784138 /* regdef:GR64 */, def dead $rdi, 2147549193 /* reguse tiedto:$1 */, killed $rdi(tied-def 5), 2147483657 /* reguse tiedto:$0 */, killed $rsi(tied-def 3), 12 /* clobber */, implicit-def dead early-clobber $eflags
- INLINEASM &foo, 0, 4784138, def $rsi, 4784138, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
+ ; CHECK: INLINEASM &foo, 0 /* attdialect */, 4390922 /* regdef:GR64 */, def $rsi, 4390922 /* regdef:GR64 */, def dead $rdi, 2147549193 /* reguse tiedto:$1 */, killed $rdi(tied-def 5), 2147483657 /* reguse tiedto:$0 */, killed $rsi(tied-def 3), 12 /* clobber */, implicit-def dead early-clobber $eflags
+ INLINEASM &foo, 0, 4390922, def $rsi, 4390922, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
$rax = MOV64rr killed $rsi
RET64 killed $rax
...
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index d3c0da9862245..6f6a24b12176f 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -6930,18 +6930,14 @@ Key: PhyReg_VK2PAIR: [ 0.00 0.00 ]
Key: PhyReg_VK4PAIR: [ 0.00 0.00 ]
Key: PhyReg_VK8PAIR: [ 0.00 0.00 ]
Key: PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: PhyReg_LOW32_ADDR_ACCESS: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit: [ 0.00 0.00 ]
Key: PhyReg_FR32X: [ 0.00 0.00 ]
Key: PhyReg_GR32: [ 0.50 0.50 ]
Key: PhyReg_GR32_NOSP: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2: [ 0.00 0.00 ]
Key: PhyReg_DEBUG_REG: [ 0.00 0.00 ]
Key: PhyReg_FR32: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX2: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX2_NOSP: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX: [ 0.00 0.00 ]
Key: PhyReg_VK32: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX_NOSP: [ 0.00 0.00 ]
@@ -6958,7 +6954,6 @@ Key: PhyReg_GR32_CB: [ 0.00 0.00 ]
Key: PhyReg_GR32_DC: [ 0.00 0.00 ]
Key: PhyReg_GR32_DIBP: [ 0.00 0.00 ]
Key: PhyReg_GR32_SIDI: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit: [ 0.00 0.00 ]
Key: PhyReg_CCR: [ 0.00 0.00 ]
Key: PhyReg_DFCCR: [ 0.00 0.00 ]
Key: PhyReg_GR32_ABCD_and_GR32_BSI: [ 0.00 0.00 ]
@@ -6968,7 +6963,6 @@ Key: PhyReg_GR32_BPSP_and_GR32_DIBP: [ 0.00 0.00 ]
Key: PhyReg_GR32_BPSP_and_GR32_TC: [ 0.00 0.00 ]
Key: PhyReg_GR32_BSI_and_GR32_SIDI: [ 0.00 0.00 ]
Key: PhyReg_GR32_DIBP_and_GR32_SIDI: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit: [ 0.00 0.00 ]
Key: PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit: [ 0.00 0.00 ]
Key: PhyReg_RFP64: [ 0.00 0.00 ]
Key: PhyReg_GR64: [ 0.60 0.60 ]
@@ -7007,7 +7001,6 @@ Key: PhyReg_GR64_with_sub_32bit_in_GR32_TC: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC: [ 0.00 0.00 ]
Key: PhyReg_GR64_AD: [ 0.00 0.00 ]
Key: PhyReg_GR64_ArgRef: [ 0.00 0.00 ]
-Key: PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_BPSP: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_BSI: [ 0.00 0.00 ]
@@ -7066,18 +7059,14 @@ Key: VirtReg_VK2PAIR: [ 0.00 0.00 ]
Key: VirtReg_VK4PAIR: [ 0.00 0.00 ]
Key: VirtReg_VK8PAIR: [ 0.00 0.00 ]
Key: VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: VirtReg_LOW32_ADDR_ACCESS: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit: [ 0.00 0.00 ]
Key: VirtReg_FR32X: [ 0.00 0.00 ]
Key: VirtReg_GR32: [ 0.80 0.80 ]
Key: VirtReg_GR32_NOSP: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2: [ 0.00 0.00 ]
Key: VirtReg_DEBUG_REG: [ 0.00 0.00 ]
Key: VirtReg_FR32: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX2: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX2_NOSP: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX: [ 0.00 0.00 ]
Key: VirtReg_VK32: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX_NOSP: [ 0.00 0.00 ]
@@ -7094,7 +7083,6 @@ Key: VirtReg_GR32_CB: [ 0.00 0.00 ]
Key: VirtReg_GR32_DC: [ 0.00 0.00 ]
Key: VirtReg_GR32_DIBP: [ 0.00 0.00 ]
Key: VirtReg_GR32_SIDI: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit: [ 0.00 0.00 ]
Key: VirtReg_CCR: [ 0.00 0.00 ]
Key: VirtReg_DFCCR: [ 0.00 0.00 ]
Key: VirtReg_GR32_ABCD_and_GR32_BSI: [ 0.00 0.00 ]
@@ -7104,7 +7092,6 @@ Key: VirtReg_GR32_BPSP_and_GR32_DIBP: [ 0.00 0.00 ]
Key: VirtReg_GR32_BPSP_and_GR32_TC: [ 0.00 0.00 ]
Key: VirtReg_GR32_BSI_and_GR32_SIDI: [ 0.00 0.00 ]
Key: VirtReg_GR32_DIBP_and_GR32_SIDI: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit: [ 0.00 0.00 ]
Key: VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit: [ 0.00 0.00 ]
Key: VirtReg_RFP64: [ 0.00 0.00 ]
Key: VirtReg_GR64: [ 0.90 0.90 ]
@@ -7143,7 +7130,6 @@ Key: VirtReg_GR64_with_sub_32bit_in_GR32_TC: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC: [ 0.00 0.00 ]
Key: VirtReg_GR64_AD: [ 0.00 0.00 ]
Key: VirtReg_GR64_ArgRef: [ 0.00 0.00 ]
-Key: VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_BPSP: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_BSI: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index c6e5508248b9b..e6ddc5b319327 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -6930,18 +6930,14 @@ Key: PhyReg_VK2PAIR: [ 0.00 0.00 ]
Key: PhyReg_VK4PAIR: [ 0.00 0.00 ]
Key: PhyReg_VK8PAIR: [ 0.00 0.00 ]
Key: PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: PhyReg_LOW32_ADDR_ACCESS: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit: [ 0.00 0.00 ]
Key: PhyReg_FR32X: [ 0.00 0.00 ]
Key: PhyReg_GR32: [ 0.50 0.50 ]
Key: PhyReg_GR32_NOSP: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2: [ 0.00 0.00 ]
Key: PhyReg_DEBUG_REG: [ 0.00 0.00 ]
Key: PhyReg_FR32: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX2: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX2_NOSP: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX: [ 0.00 0.00 ]
Key: PhyReg_VK32: [ 0.00 0.00 ]
Key: PhyReg_GR32_NOREX_NOSP: [ 0.00 0.00 ]
@@ -6958,7 +6954,6 @@ Key: PhyReg_GR32_CB: [ 0.00 0.00 ]
Key: PhyReg_GR32_DC: [ 0.00 0.00 ]
Key: PhyReg_GR32_DIBP: [ 0.00 0.00 ]
Key: PhyReg_GR32_SIDI: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit: [ 0.00 0.00 ]
Key: PhyReg_CCR: [ 0.00 0.00 ]
Key: PhyReg_DFCCR: [ 0.00 0.00 ]
Key: PhyReg_GR32_ABCD_and_GR32_BSI: [ 0.00 0.00 ]
@@ -6968,7 +6963,6 @@ Key: PhyReg_GR32_BPSP_and_GR32_DIBP: [ 0.00 0.00 ]
Key: PhyReg_GR32_BPSP_and_GR32_TC: [ 0.00 0.00 ]
Key: PhyReg_GR32_BSI_and_GR32_SIDI: [ 0.00 0.00 ]
Key: PhyReg_GR32_DIBP_and_GR32_SIDI: [ 0.00 0.00 ]
-Key: PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit: [ 0.00 0.00 ]
Key: PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit: [ 0.00 0.00 ]
Key: PhyReg_RFP64: [ 0.00 0.00 ]
Key: PhyReg_GR64: [ 0.60 0.60 ]
@@ -7007,7 +7001,6 @@ Key: PhyReg_GR64_with_sub_32bit_in_GR32_TC: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC: [ 0.00 0.00 ]
Key: PhyReg_GR64_AD: [ 0.00 0.00 ]
Key: PhyReg_GR64_ArgRef: [ 0.00 0.00 ]
-Key: PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_BPSP: [ 0.00 0.00 ]
Key: PhyReg_GR64_with_sub_32bit_in_GR32_BSI: [ 0.00 0.00 ]
@@ -7066,18 +7059,14 @@ Key: VirtReg_VK2PAIR: [ 0.00 0.00 ]
Key: VirtReg_VK4PAIR: [ 0.00 0.00 ]
Key: VirtReg_VK8PAIR: [ 0.00 0.00 ]
Key: VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: VirtReg_LOW32_ADDR_ACCESS: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit: [ 0.00 0.00 ]
Key: VirtReg_FR32X: [ 0.00 0.00 ]
Key: VirtReg_GR32: [ 0.80 0.80 ]
Key: VirtReg_GR32_NOSP: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2: [ 0.00 0.00 ]
Key: VirtReg_DEBUG_REG: [ 0.00 0.00 ]
Key: VirtReg_FR32: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX2: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX2_NOSP: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX: [ 0.00 0.00 ]
Key: VirtReg_VK32: [ 0.00 0.00 ]
Key: VirtReg_GR32_NOREX_NOSP: [ 0.00 0.00 ]
@@ -7094,7 +7083,6 @@ Key: VirtReg_GR32_CB: [ 0.00 0.00 ]
Key: VirtReg_GR32_DC: [ 0.00 0.00 ]
Key: VirtReg_GR32_DIBP: [ 0.00 0.00 ]
Key: VirtReg_GR32_SIDI: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit: [ 0.00 0.00 ]
Key: VirtReg_CCR: [ 0.00 0.00 ]
Key: VirtReg_DFCCR: [ 0.00 0.00 ]
Key: VirtReg_GR32_ABCD_and_GR32_BSI: [ 0.00 0.00 ]
@@ -7104,7 +7092,6 @@ Key: VirtReg_GR32_BPSP_and_GR32_DIBP: [ 0.00 0.00 ]
Key: VirtReg_GR32_BPSP_and_GR32_TC: [ 0.00 0.00 ]
Key: VirtReg_GR32_BSI_and_GR32_SIDI: [ 0.00 0.00 ]
Key: VirtReg_GR32_DIBP_and_GR32_SIDI: [ 0.00 0.00 ]
-Key: VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit: [ 0.00 0.00 ]
Key: VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit: [ 0.00 0.00 ]
Key: VirtReg_RFP64: [ 0.00 0.00 ]
Key: VirtReg_GR64: [ 0.90 0.90 ]
@@ -7143,7 +7130,6 @@ Key: VirtReg_GR64_with_sub_32bit_in_GR32_TC: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC: [ 0.00 0.00 ]
Key: VirtReg_GR64_AD: [ 0.00 0.00 ]
Key: VirtReg_GR64_ArgRef: [ 0.00 0.00 ]
-Key: VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_BPSP: [ 0.00 0.00 ]
Key: VirtReg_GR64_with_sub_32bit_in_GR32_BSI: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
index 41e1b5bf22bf1..cf27eec0c5873 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
@@ -30,24 +31,23 @@
...
---
name: test_copy
-# ALL-LABEL: name: test_copy
alignment: 16
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
-# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0:gr8 = COPY $al
-# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
-# ALL-NEXT: $eax = COPY %1
-# ALL-NEXT: RET 0, implicit $eax
body: |
bb.1 (%ir-block.0):
liveins: $eax
+ ; ALL-LABEL: name: test_copy
+ ; ALL: liveins: $eax
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $al
+ ; ALL-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
+ ; ALL-NEXT: $eax = COPY [[MOVZX32rr8_]]
+ ; ALL-NEXT: RET 0, implicit $eax
%0(s8) = COPY $al
%1(s32) = G_ZEXT %0(s8)
$eax = COPY %1(s32)
@@ -56,24 +56,23 @@ body: |
...
---
name: test_copy2
-# ALL-LABEL: name: test_copy2
alignment: 16
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
-# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
-# ALL: %0:gr8 = COPY $al
-# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
-# ALL-NEXT: $eax = COPY %1
-# ALL-NEXT: RET 0, implicit $eax
body: |
bb.1 (%ir-block.0):
liveins: $eax
+ ; ALL-LABEL: name: test_copy2
+ ; ALL: liveins: $eax
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $al
+ ; ALL-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
+ ; ALL-NEXT: $eax = COPY [[MOVZX32rr8_]]
+ ; ALL-NEXT: RET 0, implicit $eax
%0(s8) = COPY $al
%1(s32) = G_ZEXT %0(s8)
$eax = COPY %1(s32)
@@ -82,30 +81,35 @@ body: |
...
---
name: test_copy3
-# ALL-LABEL: name: test_copy3
alignment: 16
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] }
-# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] }
-# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
-# ALL: %0:gr16 = COPY $ax
-# X32-NEXT: %3:gr16_abcd = COPY %0
-# X32-NEXT: %1:gr8_abcd_l = COPY %3.sub_8bit
-# X64-NEXT: %1:gr8 = COPY %0.sub_8bit
-# ALL-NEXT: %2:gr32 = MOVZX32rr8 %1
-# ALL-NEXT: $eax = COPY %2
-# ALL-NEXT: RET 0, implicit $eax
body: |
bb.1 (%ir-block.0):
liveins: $eax
+ ; X32-LABEL: name: test_copy3
+ ; X32: liveins: $eax
+ ; X32-NEXT: {{ $}}
+ ; X32-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+ ; X32-NEXT: [[COPY1:%[0-9]+]]:gr16_abcd = COPY [[COPY]]
+ ; X32-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
+ ; X32-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
+ ; X32-NEXT: $eax = COPY [[MOVZX32rr8_]]
+ ; X32-NEXT: RET 0, implicit $eax
+ ;
+ ; X64-LABEL: name: test_copy3
+ ; X64: liveins: $eax
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+ ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
+ ; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
+ ; X64-NEXT: RET 0, implicit $eax
%0(s16) = COPY $ax
%1(s8) = G_TRUNC %0(s16)
%2(s32) = G_ZEXT %1(s8)
@@ -115,27 +119,25 @@ body: |
...
---
name: test_copy4
-# ALL-LABEL: name: test_copy4
alignment: 16
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
-# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
-# ALL: %0:gr32 = COPY $eax
-# ALL-NEXT: %1:gr16 = COPY %0.sub_16bit
-# ALL-NEXT: %2:gr32 = MOVZX32rr16 %1
-# ALL-NEXT: $eax = COPY %2
-# ALL-NEXT: RET 0, implicit $eax
body: |
bb.1 (%ir-block.0):
liveins: $eax
+ ; ALL-LABEL: name: test_copy4
+ ; ALL: liveins: $eax
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; ALL-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
+ ; ALL-NEXT: $eax = COPY [[MOVZX32rr16_]]
+ ; ALL-NEXT: RET 0, implicit $eax
%0(s32) = COPY $eax
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s16)
@@ -145,30 +147,35 @@ body: |
...
---
name: test_copy5
-# ALL-LABEL: name: test_copy5
alignment: 16
legalized: true
regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] }
-# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] }
-# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
-# ALL: %0:gr32 = COPY $edx
-# X32-NEXT: %3:gr32_abcd = COPY %0
-# X32-NEXT: %1:gr8_abcd_l = COPY %3.sub_8bit
-# X64-NEXT: %1:gr8 = COPY %0.sub_8bit
-# ALL-NEXT: %2:gr32 = MOVZX32rr8 %1
-# ALL-NEXT: $eax = COPY %2
-# ALL-NEXT: RET 0, implicit $eax
body: |
bb.1 (%ir-block.0):
liveins: $eax,$edx
+ ; X32-LABEL: name: test_copy5
+ ; X32: liveins: $eax, $edx
+ ; X32-NEXT: {{ $}}
+ ; X32-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/165018
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