[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Brandon Wu via llvm-commits]

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@@ -8134,6 +8233,17 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     auto *Store = cast<StoreSDNode>(Op);
     SDValue StoredVal = Store->getValue();
     EVT VT = StoredVal.getValueType();
+    if (Subtarget.hasStdExtP()) {
+      if (VT == MVT::v2i16 || VT == MVT::v4i8) {
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4vtomat wrote:

Umm seems default type legalizer `bitcast` widen vector to make its element mem type(e.g. v4i16 -> v2i32) and `extract_vector_elt` rather than just `bitcast` to `i32`

https://github.com/llvm/llvm-project/pull/162668