[llvm] [AArch64] Optimize splat of extending loads to avoid GPR->FPR transfer (PR #163067)

[David Green via llvm-commits]

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@@ -26665,11 +26665,34 @@ static SDValue performDUPCombine(SDNode *N,
   }
 
   if (N->getOpcode() == AArch64ISD::DUP) {
+    SDValue Op = N->getOperand(0);
+
+    // Optimize DUP(extload/zextload i8/i16) to avoid GPR->FPR transfer.
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davemgreen wrote:

i8/i16/i32

https://github.com/llvm/llvm-project/pull/163067