[llvm] [AMDGPU] misched: avoid subregister dependencies (PR #140255)

[Jay Foad via llvm-commits]

jayfoad wrote:

A cleaner way to implement this would be to change the MachineInstr representation of these instructions so that the def/use operands represent only the registers (or only the 32-bit parts of 64-bit register tuples) that are actually read/written by the instruction. Then you would not need this extensive hacking in `adjustSchedDependency`. This is analogous to what was done in #114500 et al for D16 loads - the pseudo models them as writing to a 16-bit VGPR, and then very late in AMDGPUMCInstLower they are lowered to the appropriate _d16 or _d16_hi form of the instruction, which has a 32-bit VGPR result but only modifies the low/high half of it.

https://github.com/llvm/llvm-project/pull/140255