[llvm] [LoongArch][NFC] Pre-commit tests for `[x]vpermi.w` (PR #164944)

[via llvm-commits]

https://github.com/zhaoqi5 created https://github.com/llvm/llvm-project/pull/164944

None

>From 1c660b1b7ef4cc865846fdd1905750e00a2d5a16 Mon Sep 17 00:00:00 2001
From: Qi Zhao <zhaoqi01 at loongson.cn>
Date: Fri, 24 Oct 2025 16:45:36 +0800
Subject: [PATCH] [LoongArch][NFC] Pre-commit tests for `[x]vpermi.w`

---
 .../lasx/ir-instruction/shuffle-as-xvpermi.ll | 41 +++++++++++++++++++
 .../lsx/ir-instruction/shuffle-as-vpermi.ll   | 41 +++++++++++++++++++
 2 files changed, 82 insertions(+)
 create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll

diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
new file mode 100644
index 0000000000000..f73f7a659abed
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+;; xvpermi.w
+define void @shufflevector_xvpermi_v8i32(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_xvpermi_v8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a1, 0
+; CHECK-NEXT:    xvld $xr1, $a2, 0
+; CHECK-NEXT:    xvbsrl.v $xr0, $xr0, 8
+; CHECK-NEXT:    xvbsll.v $xr1, $xr1, 8
+; CHECK-NEXT:    xvor.v $xr0, $xr1, $xr0
+; CHECK-NEXT:    xvst $xr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <8 x i32>, ptr %a
+  %vb = load <8 x i32>, ptr %b
+  %c = shufflevector <8 x i32> %va, <8 x i32> %vb, <8 x i32> <i32 2, i32 3, i32 8, i32 9, i32 6, i32 7, i32 12, i32 13>
+  store <8 x i32> %c, ptr %res
+  ret void
+}
+
+;; xvpermi.w
+define void @shufflevector_xvpermi_v8f32(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_xvpermi_v8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvld $xr0, $a1, 0
+; CHECK-NEXT:    xvld $xr1, $a2, 0
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT:    xvld $xr2, $a1, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT:    xvshuf.w $xr2, $xr1, $xr0
+; CHECK-NEXT:    xvst $xr2, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <8 x float>, ptr %a
+  %vb = load <8 x float>, ptr %b
+  %c = shufflevector <8 x float> %va, <8 x float> %vb, <8 x i32> <i32 9, i32 11, i32 0, i32 2, i32 13, i32 15, i32 4, i32 6>
+  store <8 x float> %c, ptr %res
+  ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll
new file mode 100644
index 0000000000000..ca65dd87f6c61
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+;; vpermi.w
+define void @shufflevector_vpermi_v4i32(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_vpermi_v4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    vbsrl.v $vr0, $vr0, 8
+; CHECK-NEXT:    vbsll.v $vr1, $vr1, 8
+; CHECK-NEXT:    vor.v $vr0, $vr1, $vr0
+; CHECK-NEXT:    vst $vr0, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <4 x i32>, ptr %a
+  %vb = load <4 x i32>, ptr %b
+  %c = shufflevector <4 x i32> %va, <4 x i32> %vb, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+  store <4 x i32> %c, ptr %res
+  ret void
+}
+
+;; vpermi.w
+define void @shufflevector_vpermi_v4f32(ptr %res, ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: shufflevector_vpermi_v4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vld $vr0, $a1, 0
+; CHECK-NEXT:    vld $vr1, $a2, 0
+; CHECK-NEXT:    pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT:    vld $vr2, $a1, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT:    vshuf.w $vr2, $vr1, $vr0
+; CHECK-NEXT:    vst $vr2, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %va = load <4 x float>, ptr %a
+  %vb = load <4 x float>, ptr %b
+  %c = shufflevector <4 x float> %va, <4 x float> %vb, <4 x i32> <i32 5, i32 7, i32 0, i32 2>
+  store <4 x float> %c, ptr %res
+  ret void
+}