[llvm] [X86][ISel] Improve VPTERNLOG matching for negated logic trees (PR #164863)

[Phoebe Wang via llvm-commits]

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@@ -4740,6 +4737,35 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
     return SDValue();
   };
 
+  // Identify and (optionally) peel an outer NOT that wraps a pure logic tree
+  auto tryPeelOuterNotWrappingLogic = [&](SDNode *Op) {
+    if (Op->getOpcode() == ISD::XOR && Op->hasOneUse() &&
+        ISD::isBuildVectorAllOnes(Op->getOperand(1).getNode())) {
+      SDNode *InnerN = Op->getOperand(0).getNode();
+
+      unsigned InnerOpc = InnerN->getOpcode();
+      if (InnerOpc != ISD::AND && InnerOpc != ISD::OR && InnerOpc != ISD::XOR &&
+          InnerOpc != X86ISD::ANDNP) {
+        return Op;
+      }
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phoebewang wrote:

if (getFoldableLogicOp(InnerOp))?

https://github.com/llvm/llvm-project/pull/164863