[llvm] [X86][ISel] Improve VPTERNLOG matching for negated logic trees (PR #164863)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 06a691d73..ab86901c2 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -4744,8 +4744,8 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
       SDNode *InnerN = Op->getOperand(0).getNode();
 
       unsigned InnerOpc = InnerN->getOpcode();
-      if (InnerOpc != ISD::AND && InnerOpc != ISD::OR &&
-          InnerOpc != ISD::XOR && InnerOpc != X86ISD::ANDNP) {
+      if (InnerOpc != ISD::AND && InnerOpc != ISD::OR && InnerOpc != ISD::XOR &&
+          InnerOpc != X86ISD::ANDNP) {
         return Op;
       }
 
@@ -4763,7 +4763,6 @@ bool X86DAGToDAGISel::tryVPTERNLOG(SDNode *N) {
   N = tryPeelOuterNotWrappingLogic(N);
   if (N != OriN)
     PeeledOuterNot = true;
-    
 
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);

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https://github.com/llvm/llvm-project/pull/164863