[llvm] 10bec2c - [llvm-ir2vec][MIR2Vec] Supporting MIR mode in triplet and entity generation (#164329)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 23 10:51:29 PDT 2025
Author: S. VenkataKeerthy
Date: 2025-10-23T10:51:24-07:00
New Revision: 10bec2cd9dab796d5685fa8aadf47b912e3558fe
URL: https://github.com/llvm/llvm-project/commit/10bec2cd9dab796d5685fa8aadf47b912e3558fe
DIFF: https://github.com/llvm/llvm-project/commit/10bec2cd9dab796d5685fa8aadf47b912e3558fe.diff
LOG: [llvm-ir2vec][MIR2Vec] Supporting MIR mode in triplet and entity generation (#164329)
Add support for Machine IR (MIR) triplet and entity generation in llvm-ir2vec.
This change extends llvm-ir2vec to support Machine IR (MIR) in addition to LLVM IR, enabling the generation of training data for MIR2Vec embeddings. MIR2Vec provides machine-level code embeddings that capture target-specific instruction semantics, complementing the target-independent IR2Vec embeddings.
- Extended llvm-ir2vec to support triplet and entity generation for Machine IR (MIR)
- Added `--mode=mir` option to specify MIR mode (vs LLVM IR mode)
- Implemented MIR triplet generation with Next and Arg relationships
- Added entity mapping generation for MIR vocabulary
- Updated documentation to explain MIR-specific features and usage
(Partially addresses #162200 ; Tracking issue - #141817)
Added:
llvm/test/tools/llvm-ir2vec/entities.mir
llvm/test/tools/llvm-ir2vec/output/lit.local.cfg
llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
llvm/test/tools/llvm-ir2vec/triplets.mir
Modified:
llvm/docs/CommandGuide/llvm-ir2vec.rst
llvm/include/llvm/CodeGen/MIR2Vec.h
llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
Removed:
################################################################################
diff --git a/llvm/docs/CommandGuide/llvm-ir2vec.rst b/llvm/docs/CommandGuide/llvm-ir2vec.rst
index 55fe75d2084b1..f51da065b43d8 100644
--- a/llvm/docs/CommandGuide/llvm-ir2vec.rst
+++ b/llvm/docs/CommandGuide/llvm-ir2vec.rst
@@ -68,32 +68,52 @@ these two modes are used to generate the triplets and entity mappings.
Triplet Generation
~~~~~~~~~~~~~~~~~~
-With the `triplets` subcommand, :program:`llvm-ir2vec` analyzes LLVM IR and extracts
-numeric triplets consisting of opcode IDs, type IDs, and operand IDs. These triplets
+With the `triplets` subcommand, :program:`llvm-ir2vec` analyzes LLVM IR or Machine IR
+and extracts numeric triplets consisting of opcode IDs and operand IDs. These triplets
are generated in the standard format used for knowledge graph embedding training.
-The tool outputs numeric IDs directly using the ir2vec::Vocabulary mapping
-infrastructure, eliminating the need for string-to-ID preprocessing.
+The tool outputs numeric IDs directly using the vocabulary mapping infrastructure,
+eliminating the need for string-to-ID preprocessing.
-Usage:
+Usage for LLVM IR:
.. code-block:: bash
- llvm-ir2vec triplets input.bc -o triplets_train2id.txt
+ llvm-ir2vec triplets --mode=llvm input.bc -o triplets_train2id.txt
+
+Usage for Machine IR:
+
+.. code-block:: bash
+
+ llvm-ir2vec triplets --mode=mir input.mir -o triplets_train2id.txt
Entity Mapping Generation
~~~~~~~~~~~~~~~~~~~~~~~~~
With the `entities` subcommand, :program:`llvm-ir2vec` generates the entity mappings
-supported by IR2Vec in the standard format used for knowledge graph embedding
-training. This subcommand outputs all supported entities (opcodes, types, and
-operands) with their corresponding numeric IDs, and is not specific for an
-LLVM IR file.
+supported by IR2Vec or MIR2Vec in the standard format used for knowledge graph embedding
+training. This subcommand outputs all supported entities with their corresponding numeric IDs.
+
+For LLVM IR, entities include opcodes, types, and operands. For Machine IR, entities include
+machine opcodes, common operands, and register classes (both physical and virtual).
+
+Usage for LLVM IR:
-Usage:
+.. code-block:: bash
+
+ llvm-ir2vec entities --mode=llvm -o entity2id.txt
+
+Usage for Machine IR:
.. code-block:: bash
- llvm-ir2vec entities -o entity2id.txt
+ llvm-ir2vec entities --mode=mir input.mir -o entity2id.txt
+
+.. note::
+
+ For LLVM IR mode, the entity mapping is target-independent and does not require an input file.
+ For Machine IR mode, an input .mir file is required to determine the target architecture,
+ as entity mappings vary by target (
diff erent architectures have
diff erent instruction sets
+ and register classes).
Embedding Generation
~~~~~~~~~~~~~~~~~~~~
@@ -222,12 +242,17 @@ Subcommand-specific options:
.. option:: <input-file>
- The input LLVM IR or bitcode file to process. This positional argument is
- required for the `triplets` subcommand.
+ The input LLVM IR/bitcode file (.ll/.bc) or Machine IR file (.mir) to process.
+ This positional argument is required for the `triplets` subcommand.
**entities** subcommand:
- No subcommand-specific options.
+.. option:: <input-file>
+
+ The input Machine IR file (.mir) to process. This positional argument is required
+ for the `entities` subcommand when using ``--mode=mir``, as the entity mappings
+ are target-specific. For ``--mode=llvm``, no input file is required as IR2Vec
+ entity mappings are target-independent.
OUTPUT FORMAT
-------------
@@ -240,19 +265,37 @@ metadata headers. The format includes:
.. code-block:: text
- MAX_RELATIONS=<max_relations_count>
+ MAX_RELATION=<max_relation_count>
<head_entity_id> <tail_entity_id> <relation_id>
<head_entity_id> <tail_entity_id> <relation_id>
...
Each line after the metadata header represents one instruction relationship,
-with numeric IDs for head entity, relation, and tail entity. The metadata
-header (MAX_RELATIONS) provides counts for post-processing and training setup.
+with numeric IDs for head entity, tail entity, and relation type. The metadata
+header (MAX_RELATION) indicates the maximum relation ID used.
+
+**Relation Types:**
+
+For LLVM IR (IR2Vec):
+ * **0** = Type relationship (instruction to its type)
+ * **1** = Next relationship (sequential instructions)
+ * **2+** = Argument relationships (Arg0, Arg1, Arg2, ...)
+
+For Machine IR (MIR2Vec):
+ * **0** = Next relationship (sequential instructions)
+ * **1+** = Argument relationships (Arg0, Arg1, Arg2, ...)
+
+**Entity IDs:**
+
+For LLVM IR: Entity IDs represent opcodes, types, and operands as defined by the IR2Vec vocabulary.
+
+For Machine IR: Entity IDs represent machine opcodes, common operands (immediate, frame index, etc.),
+physical register classes, and virtual register classes as defined by the MIR2Vec vocabulary. The entity layout is target-specific.
Entity Mode Output
~~~~~~~~~~~~~~~~~~
-In entity mode, the output consists of entity mapping in the format:
+In entity mode, the output consists of entity mappings in the format:
.. code-block:: text
@@ -264,6 +307,13 @@ In entity mode, the output consists of entity mapping in the format:
The first line contains the total number of entities, followed by one entity
mapping per line with tab-separated entity string and numeric ID.
+For LLVM IR, entities include instruction opcodes (e.g., "Add", "Ret"), types
+(e.g., "INT", "PTR"), and operand kinds.
+
+For Machine IR, entities include machine opcodes (e.g., "COPY", "ADD"),
+common operands (e.g., "Immediate", "FrameIndex"), physical register classes
+(e.g., "PhyReg_GR32"), and virtual register classes (e.g., "VirtReg_GR32").
+
Embedding Mode Output
~~~~~~~~~~~~~~~~~~~~~
diff --git a/llvm/include/llvm/CodeGen/MIR2Vec.h b/llvm/include/llvm/CodeGen/MIR2Vec.h
index 48bb0a5f2fed9..44f009cd7790e 100644
--- a/llvm/include/llvm/CodeGen/MIR2Vec.h
+++ b/llvm/include/llvm/CodeGen/MIR2Vec.h
@@ -111,6 +111,11 @@ class MIRVocabulary {
size_t TotalEntries = 0;
} Layout;
+ // TODO: See if we can have only one reg classes section instead of physical
+ // and virtual separate sections in the vocabulary. This would reduce the
+ // number of vocabulary entities significantly.
+ // We can potentially distinguish physical and virtual registers by
+ // considering them as a separate feature.
enum class Section : unsigned {
Opcodes = 0,
CommonOperands = 1,
@@ -185,6 +190,25 @@ class MIRVocabulary {
return Storage[static_cast<unsigned>(SectionID)][LocalIndex];
}
+ /// Get entity ID (flat index) for a common operand type
+ /// This is used for triplet generation
+ unsigned getEntityIDForCommonOperand(
+ MachineOperand::MachineOperandType OperandType) const {
+ return Layout.CommonOperandBase + getCommonOperandIndex(OperandType);
+ }
+
+ /// Get entity ID (flat index) for a register
+ /// This is used for triplet generation
+ unsigned getEntityIDForRegister(Register Reg) const {
+ if (!Reg.isValid() || Reg.isStack())
+ return Layout
+ .VirtRegBase; // Return VirtRegBase for invalid/stack registers
+ unsigned LocalIndex = getRegisterOperandIndex(Reg);
+ size_t BaseOffset =
+ Reg.isPhysical() ? Layout.PhyRegBase : Layout.VirtRegBase;
+ return BaseOffset + LocalIndex;
+ }
+
public:
/// Static method for extracting base opcode names (public for testing)
static std::string extractBaseOpcodeName(StringRef InstrName);
@@ -201,6 +225,20 @@ class MIRVocabulary {
unsigned getDimension() const { return Storage.getDimension(); }
+ /// Get entity ID (flat index) for an opcode
+ /// This is used for triplet generation
+ unsigned getEntityIDForOpcode(unsigned Opcode) const {
+ return Layout.OpcodeBase + getCanonicalOpcodeIndex(Opcode);
+ }
+
+ /// Get entity ID (flat index) for a machine operand
+ /// This is used for triplet generation
+ unsigned getEntityIDForMachineOperand(const MachineOperand &MO) const {
+ if (MO.getType() == MachineOperand::MO_Register)
+ return getEntityIDForRegister(MO.getReg());
+ return getEntityIDForCommonOperand(MO.getType());
+ }
+
// Accessor methods
const Embedding &operator[](unsigned Opcode) const {
unsigned LocalIndex = getCanonicalOpcodeIndex(Opcode);
diff --git a/llvm/test/tools/llvm-ir2vec/entities.mir b/llvm/test/tools/llvm-ir2vec/entities.mir
new file mode 100644
index 0000000000000..60d9c7a783c4c
--- /dev/null
+++ b/llvm/test/tools/llvm-ir2vec/entities.mir
@@ -0,0 +1,28 @@
+# REQUIRES: x86_64-linux
+# RUN: llvm-ir2vec entities --mode=mir %s -o 2>&1 %t1.log
+# RUN:
diff %S/output/reference_x86_entities.txt %t1.log
+
+--- |
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-unknown-linux-gnu"
+
+ define dso_local noundef i32 @test_function(i32 noundef %a) {
+ entry:
+ ret i32 %a
+ }
+...
+---
+name: test_function
+alignment: 16
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+liveins:
+ - { reg: '$edi', virtual-reg: '%0' }
+body: |
+ bb.0.entry:
+ liveins: $edi
+
+ %0:gr32 = COPY $edi
+ $eax = COPY %0
+ RET 0, $eax
diff --git a/llvm/test/tools/llvm-ir2vec/output/lit.local.cfg b/llvm/test/tools/llvm-ir2vec/output/lit.local.cfg
new file mode 100644
index 0000000000000..2406f19eebcdd
--- /dev/null
+++ b/llvm/test/tools/llvm-ir2vec/output/lit.local.cfg
@@ -0,0 +1,3 @@
+# Don't treat files in this directory as tests
+# These are reference data files, not test scripts
+config.suffixes = []
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
new file mode 100644
index 0000000000000..dfbac4ce0c4d3
--- /dev/null
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
@@ -0,0 +1,33 @@
+MAX_RELATION=4
+187 7072 1
+187 6968 2
+187 187 0
+187 7072 1
+187 6969 2
+187 10 0
+10 7072 1
+10 7072 2
+10 7072 3
+10 6961 4
+10 187 0
+187 6952 1
+187 7072 2
+187 1555 0
+1555 6882 1
+1555 6952 2
+187 7072 1
+187 6968 2
+187 187 0
+187 7072 1
+187 6969 2
+187 601 0
+601 7072 1
+601 7072 2
+601 7072 3
+601 6961 4
+601 187 0
+187 6952 1
+187 7072 2
+187 1555 0
+1555 6882 1
+1555 6952 2
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
new file mode 100644
index 0000000000000..dc436d123fd35
--- /dev/null
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
@@ -0,0 +1,7174 @@
+7173
+AAA 0
+AAD 1
+AADD 2
+AAM 3
+AAND 4
+AAS 5
+ABS_F 6
+ABS_Fp 7
+ADC 8
+ADCX 9
+ADD 10
+ADDPDrm 11
+ADDPDrr 12
+ADDPSrm 13
+ADDPSrr 14
+ADDR 15
+ADDSDrm 16
+ADDSDrm_Int 17
+ADDSDrr 18
+ADDSDrr_Int 19
+ADDSSrm 20
+ADDSSrm_Int 21
+ADDSSrr 22
+ADDSSrr_Int 23
+ADDSUBPDrm 24
+ADDSUBPDrr 25
+ADDSUBPSrm 26
+ADDSUBPSrr 27
+ADD_F 28
+ADD_FI 29
+ADD_FPrST 30
+ADD_FST 31
+ADD_Fp 32
+ADD_FpI 33
+ADD_FrST 34
+ADJCALLSTACKDOWN 35
+ADJCALLSTACKUP 36
+ADOX 37
+AESDEC 38
+AESDECLASTrm 39
+AESDECLASTrr 40
+AESDECWIDE 41
+AESDECrm 42
+AESDECrr 43
+AESENC 44
+AESENCLASTrm 45
+AESENCLASTrr 46
+AESENCWIDE 47
+AESENCrm 48
+AESENCrr 49
+AESIMCrm 50
+AESIMCrr 51
+AESKEYGENASSISTrmi 52
+AESKEYGENASSISTrri 53
+AND 54
+ANDN 55
+ANDNPDrm 56
+ANDNPDrr 57
+ANDNPSrm 58
+ANDNPSrr 59
+ANDPDrm 60
+ANDPDrr 61
+ANDPSrm 62
+ANDPSrr 63
+ANNOTATION_LABEL 64
+AOR 65
+ARITH_FENCE 66
+ARPL 67
+ASAN_CHECK_MEMACCESS 68
+AVX 69
+AVX_SET 70
+AXOR 71
+BEXTR 72
+BEXTRI 73
+BLCFILL 74
+BLCI 75
+BLCIC 76
+BLCMSK 77
+BLCS 78
+BLENDPDrmi 79
+BLENDPDrri 80
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+BLENDVPDrm 83
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+BLENDVPSrm 85
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+BLSFILL 87
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+BLSIC 89
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+BT 96
+BTC 97
+BTR 98
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+BUNDLE 100
+BZHI 101
+CALL 102
+CALLpcrel 103
+CATCHRET 104
+CBW 105
+CCMP 106
+CDQ 107
+CDQE 108
+CFCMOV 109
+CFI_INSTRUCTION 110
+CHS_F 111
+CHS_Fp 112
+CLAC 113
+CLC 114
+CLD 115
+CLDEMOTE 116
+CLEANUPRET 117
+CLFLUSH 118
+CLFLUSHOPT 119
+CLGI 120
+CLI 121
+CLRSSBSY 122
+CLTS 123
+CLUI 124
+CLWB 125
+CLZERO 126
+CMC 127
+CMOV 128
+CMOVBE_F 129
+CMOVBE_Fp 130
+CMOVB_F 131
+CMOVB_Fp 132
+CMOVE_F 133
+CMOVE_Fp 134
+CMOVNBE_F 135
+CMOVNBE_Fp 136
+CMOVNB_F 137
+CMOVNB_Fp 138
+CMOVNE_F 139
+CMOVNE_Fp 140
+CMOVNP_F 141
+CMOVNP_Fp 142
+CMOVP_F 143
+CMOVP_Fp 144
+CMOV_FR 145
+CMOV_GR 146
+CMOV_RFP 147
+CMOV_VK 148
+CMOV_VR 149
+CMP 150
+CMPCCXADDmr 151
+CMPPDrmi 152
+CMPPDrri 153
+CMPPSrmi 154
+CMPPSrri 155
+CMPSB 156
+CMPSDrmi 157
+CMPSDrmi_Int 158
+CMPSDrri 159
+CMPSDrri_Int 160
+CMPSL 161
+CMPSQ 162
+CMPSSrmi 163
+CMPSSrmi_Int 164
+CMPSSrri 165
+CMPSSrri_Int 166
+CMPSW 167
+CMPXCHG 168
+COMISDrm 169
+COMISDrm_Int 170
+COMISDrr 171
+COMISDrr_Int 172
+COMISSrm 173
+COMISSrm_Int 174
+COMISSrr 175
+COMISSrr_Int 176
+COMP_FST 177
+COM_FIPr 178
+COM_FIr 179
+COM_FST 180
+COM_FpIr 181
+COM_Fpr 182
+CONVERGENCECTRL_ANCHOR 183
+CONVERGENCECTRL_ENTRY 184
+CONVERGENCECTRL_GLUE 185
+CONVERGENCECTRL_LOOP 186
+COPY 187
+COPY_TO_REGCLASS 188
+CPUID 189
+CQO 190
+CRC 191
+CS_PREFIX 192
+CTEST 193
+CVTDQ 194
+CVTPD 195
+CVTPS 196
+CVTSD 197
+CVTSI 198
+CVTSS 199
+CVTTPD 200
+CVTTPS 201
+CVTTSD 202
+CVTTSS 203
+CWD 204
+CWDE 205
+DAA 206
+DAS 207
+DATA 208
+DBG_INSTR_REF 209
+DBG_LABEL 210
+DBG_PHI 211
+DBG_VALUE 212
+DBG_VALUE_LIST 213
+DEC 214
+DIV 215
+DIVPDrm 216
+DIVPDrr 217
+DIVPSrm 218
+DIVPSrr 219
+DIVR_F 220
+DIVR_FI 221
+DIVR_FPrST 222
+DIVR_FST 223
+DIVR_Fp 224
+DIVR_FpI 225
+DIVR_FrST 226
+DIVSDrm 227
+DIVSDrm_Int 228
+DIVSDrr 229
+DIVSDrr_Int 230
+DIVSSrm 231
+DIVSSrm_Int 232
+DIVSSrr 233
+DIVSSrr_Int 234
+DIV_F 235
+DIV_FI 236
+DIV_FPrST 237
+DIV_FST 238
+DIV_Fp 239
+DIV_FpI 240
+DIV_FrST 241
+DPPDrmi 242
+DPPDrri 243
+DPPSrmi 244
+DPPSrri 245
+DS_PREFIX 246
+DYN_ALLOCA 247
+EH_LABEL 248
+EH_RETURN 249
+EH_SjLj_LongJmp 250
+EH_SjLj_SetJmp 251
+EH_SjLj_Setup 252
+ENCLS 253
+ENCLU 254
+ENCLV 255
+ENCODEKEY 256
+ENDBR 257
+ENQCMD 258
+ENQCMDS 259
+ENTER 260
+ERETS 261
+ERETU 262
+ES_PREFIX 263
+EXTRACTPSmri 264
+EXTRACTPSrri 265
+EXTRACT_SUBREG 266
+EXTRQ 267
+EXTRQI 268
+F 269
+FAKE_USE 270
+FARCALL 271
+FARJMP 272
+FAULTING_OP 273
+FBLDm 274
+FBSTPm 275
+FCOM 276
+FCOMP 277
+FCOMPP 278
+FCOS 279
+FDECSTP 280
+FEMMS 281
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+FFREEP 284
+FICOM 285
+FICOMP 286
+FINCSTP 287
+FLDCW 288
+FLDENVm 289
+FLDL 290
+FLDLG 291
+FLDLN 292
+FLDPI 293
+FNCLEX 294
+FNINIT 295
+FNOP 296
+FNSTCW 297
+FNSTSW 298
+FNSTSWm 299
+FP 300
+FPATAN 301
+FPREM 302
+FPTAN 303
+FRNDINT 304
+FRSTORm 305
+FSAVEm 306
+FSCALE 307
+FSIN 308
+FSINCOS 309
+FSTENVm 310
+FS_PREFIX 311
+FXRSTOR 312
+FXSAVE 313
+FXTRACT 314
+FYL 315
+FsFLD 316
+GC_LABEL 317
+GETSEC 318
+GF 319
+GS_PREFIX 320
+G_ABDS 321
+G_ABDU 322
+G_ABS 323
+G_ADD 324
+G_ADDRSPACE_CAST 325
+G_AND 326
+G_ANYEXT 327
+G_ASHR 328
+G_ASSERT_ALIGN 329
+G_ASSERT_SEXT 330
+G_ASSERT_ZEXT 331
+G_ATOMICRMW_ADD 332
+G_ATOMICRMW_AND 333
+G_ATOMICRMW_FADD 334
+G_ATOMICRMW_FMAX 335
+G_ATOMICRMW_FMAXIMUM 336
+G_ATOMICRMW_FMIN 337
+G_ATOMICRMW_FMINIMUM 338
+G_ATOMICRMW_FSUB 339
+G_ATOMICRMW_MAX 340
+G_ATOMICRMW_MIN 341
+G_ATOMICRMW_NAND 342
+G_ATOMICRMW_OR 343
+G_ATOMICRMW_SUB 344
+G_ATOMICRMW_UDEC_WRAP 345
+G_ATOMICRMW_UINC_WRAP 346
+G_ATOMICRMW_UMAX 347
+G_ATOMICRMW_UMIN 348
+G_ATOMICRMW_USUB_COND 349
+G_ATOMICRMW_USUB_SAT 350
+G_ATOMICRMW_XCHG 351
+G_ATOMICRMW_XOR 352
+G_ATOMIC_CMPXCHG 353
+G_ATOMIC_CMPXCHG_WITH_SUCCESS 354
+G_BITCAST 355
+G_BITREVERSE 356
+G_BLOCK_ADDR 357
+G_BR 358
+G_BRCOND 359
+G_BRINDIRECT 360
+G_BRJT 361
+G_BSWAP 362
+G_BUILD_VECTOR 363
+G_BUILD_VECTOR_TRUNC 364
+G_BZERO 365
+G_CONCAT_VECTORS 366
+G_CONSTANT 367
+G_CONSTANT_FOLD_BARRIER 368
+G_CONSTANT_POOL 369
+G_CTLZ 370
+G_CTLZ_ZERO_UNDEF 371
+G_CTPOP 372
+G_CTTZ 373
+G_CTTZ_ZERO_UNDEF 374
+G_DEBUGTRAP 375
+G_DYN_STACKALLOC 376
+G_EXTRACT 377
+G_EXTRACT_SUBVECTOR 378
+G_EXTRACT_VECTOR_ELT 379
+G_FABS 380
+G_FACOS 381
+G_FADD 382
+G_FASIN 383
+G_FATAN 384
+G_FCANONICALIZE 385
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+G_FCMP 387
+G_FCONSTANT 388
+G_FCOPYSIGN 389
+G_FCOS 390
+G_FCOSH 391
+G_FDIV 392
+G_FENCE 393
+G_FEXP 394
+G_FFLOOR 395
+G_FFREXP 396
+G_FILD 397
+G_FIST 398
+G_FLDCW 399
+G_FLDEXP 400
+G_FLOG 401
+G_FMA 402
+G_FMAD 403
+G_FMAXIMUM 404
+G_FMAXIMUMNUM 405
+G_FMAXNUM 406
+G_FMAXNUM_IEEE 407
+G_FMINIMUM 408
+G_FMINIMUMNUM 409
+G_FMINNUM 410
+G_FMINNUM_IEEE 411
+G_FMODF 412
+G_FMUL 413
+G_FNEARBYINT 414
+G_FNEG 415
+G_FNSTCW 416
+G_FPEXT 417
+G_FPOW 418
+G_FPOWI 419
+G_FPTOSI 420
+G_FPTOSI_SAT 421
+G_FPTOUI 422
+G_FPTOUI_SAT 423
+G_FPTRUNC 424
+G_FRAME_INDEX 425
+G_FREEZE 426
+G_FREM 427
+G_FRINT 428
+G_FSHL 429
+G_FSHR 430
+G_FSIN 431
+G_FSINCOS 432
+G_FSINH 433
+G_FSQRT 434
+G_FSUB 435
+G_FTAN 436
+G_FTANH 437
+G_GET_FPENV 438
+G_GET_FPMODE 439
+G_GET_ROUNDING 440
+G_GLOBAL_VALUE 441
+G_ICMP 442
+G_IMPLICIT_DEF 443
+G_INDEXED_LOAD 444
+G_INDEXED_SEXTLOAD 445
+G_INDEXED_STORE 446
+G_INDEXED_ZEXTLOAD 447
+G_INSERT 448
+G_INSERT_SUBVECTOR 449
+G_INSERT_VECTOR_ELT 450
+G_INTRINSIC 451
+G_INTRINSIC_CONVERGENT 452
+G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 453
+G_INTRINSIC_FPTRUNC_ROUND 454
+G_INTRINSIC_LLRINT 455
+G_INTRINSIC_LRINT 456
+G_INTRINSIC_ROUND 457
+G_INTRINSIC_ROUNDEVEN 458
+G_INTRINSIC_TRUNC 459
+G_INTRINSIC_W_SIDE_EFFECTS 460
+G_INTTOPTR 461
+G_INVOKE_REGION_START 462
+G_IS_FPCLASS 463
+G_JUMP_TABLE 464
+G_LLROUND 465
+G_LOAD 466
+G_LROUND 467
+G_LSHR 468
+G_MEMCPY 469
+G_MEMCPY_INLINE 470
+G_MEMMOVE 471
+G_MEMSET 472
+G_MERGE_VALUES 473
+G_MUL 474
+G_OR 475
+G_PHI 476
+G_PREFETCH 477
+G_PTRAUTH_GLOBAL_VALUE 478
+G_PTRMASK 479
+G_PTRTOINT 480
+G_PTR_ADD 481
+G_READCYCLECOUNTER 482
+G_READSTEADYCOUNTER 483
+G_READ_REGISTER 484
+G_RESET_FPENV 485
+G_RESET_FPMODE 486
+G_ROTL 487
+G_ROTR 488
+G_SADDE 489
+G_SADDO 490
+G_SADDSAT 491
+G_SBFX 492
+G_SCMP 493
+G_SDIV 494
+G_SDIVFIX 495
+G_SDIVFIXSAT 496
+G_SDIVREM 497
+G_SELECT 498
+G_SET_FPENV 499
+G_SET_FPMODE 500
+G_SET_ROUNDING 501
+G_SEXT 502
+G_SEXTLOAD 503
+G_SEXT_INREG 504
+G_SHL 505
+G_SHUFFLE_VECTOR 506
+G_SITOFP 507
+G_SMAX 508
+G_SMIN 509
+G_SMULFIX 510
+G_SMULFIXSAT 511
+G_SMULH 512
+G_SMULO 513
+G_SPLAT_VECTOR 514
+G_SREM 515
+G_SSHLSAT 516
+G_SSUBE 517
+G_SSUBO 518
+G_SSUBSAT 519
+G_STACKRESTORE 520
+G_STACKSAVE 521
+G_STEP_VECTOR 522
+G_STORE 523
+G_STRICT_FADD 524
+G_STRICT_FDIV 525
+G_STRICT_FLDEXP 526
+G_STRICT_FMA 527
+G_STRICT_FMUL 528
+G_STRICT_FREM 529
+G_STRICT_FSQRT 530
+G_STRICT_FSUB 531
+G_SUB 532
+G_TRAP 533
+G_TRUNC 534
+G_TRUNC_SSAT_S 535
+G_TRUNC_SSAT_U 536
+G_TRUNC_USAT_U 537
+G_UADDE 538
+G_UADDO 539
+G_UADDSAT 540
+G_UBFX 541
+G_UBSANTRAP 542
+G_UCMP 543
+G_UDIV 544
+G_UDIVFIX 545
+G_UDIVFIXSAT 546
+G_UDIVREM 547
+G_UITOFP 548
+G_UMAX 549
+G_UMIN 550
+G_UMULFIX 551
+G_UMULFIXSAT 552
+G_UMULH 553
+G_UMULO 554
+G_UNMERGE_VALUES 555
+G_UREM 556
+G_USHLSAT 557
+G_USUBE 558
+G_USUBO 559
+G_USUBSAT 560
+G_VAARG 561
+G_VASTART 562
+G_VECREDUCE_ADD 563
+G_VECREDUCE_AND 564
+G_VECREDUCE_FADD 565
+G_VECREDUCE_FMAX 566
+G_VECREDUCE_FMAXIMUM 567
+G_VECREDUCE_FMIN 568
+G_VECREDUCE_FMINIMUM 569
+G_VECREDUCE_FMUL 570
+G_VECREDUCE_MUL 571
+G_VECREDUCE_OR 572
+G_VECREDUCE_SEQ_FADD 573
+G_VECREDUCE_SEQ_FMUL 574
+G_VECREDUCE_SMAX 575
+G_VECREDUCE_SMIN 576
+G_VECREDUCE_UMAX 577
+G_VECREDUCE_UMIN 578
+G_VECREDUCE_XOR 579
+G_VECTOR_COMPRESS 580
+G_VSCALE 581
+G_WRITE_REGISTER 582
+G_XOR 583
+G_ZEXT 584
+G_ZEXTLOAD 585
+HADDPDrm 586
+HADDPDrr 587
+HADDPSrm 588
+HADDPSrr 589
+HLT 590
+HRESET 591
+HSUBPDrm 592
+HSUBPDrr 593
+HSUBPSrm 594
+HSUBPSrr 595
+ICALL_BRANCH_FUNNEL 596
+IDIV 597
+ILD_F 598
+ILD_Fp 599
+IMPLICIT_DEF 600
+IMUL 601
+IMULZU 602
+IN 603
+INC 604
+INCSSPD 605
+INCSSPQ 606
+INDIRECT_THUNK_CALL 607
+INDIRECT_THUNK_TCRETURN 608
+INIT_UNDEF 609
+INLINEASM 610
+INLINEASM_BR 611
+INSB 612
+INSERTPSrmi 613
+INSERTPSrri 614
+INSERTQ 615
+INSERTQI 616
+INSERT_SUBREG 617
+INSL 618
+INSW 619
+INT 620
+INTO 621
+INVD 622
+INVEPT 623
+INVLPG 624
+INVLPGA 625
+INVLPGB 626
+INVPCID 627
+INVVPID 628
+IRET 629
+ISTT_FP 630
+ISTT_Fp 631
+IST_F 632
+IST_FP 633
+IST_Fp 634
+Int_eh_sjlj_setup_dispatch 635
+JCC 636
+JCXZ 637
+JECXZ 638
+JMP 639
+JMPABS 640
+JRCXZ 641
+JUMP_TABLE_DEBUG_INFO 642
+KADDBkk 643
+KADDDkk 644
+KADDQkk 645
+KADDWkk 646
+KANDBkk 647
+KANDDkk 648
+KANDNBkk 649
+KANDNDkk 650
+KANDNQkk 651
+KANDNWkk 652
+KANDQkk 653
+KANDWkk 654
+KCFI_CHECK 655
+KILL 656
+KMOVBkk 657
+KMOVBkk_EVEX 658
+KMOVBkm 659
+KMOVBkm_EVEX 660
+KMOVBkr 661
+KMOVBkr_EVEX 662
+KMOVBmk 663
+KMOVBmk_EVEX 664
+KMOVBrk 665
+KMOVBrk_EVEX 666
+KMOVDkk 667
+KMOVDkk_EVEX 668
+KMOVDkm 669
+KMOVDkm_EVEX 670
+KMOVDkr 671
+KMOVDkr_EVEX 672
+KMOVDmk 673
+KMOVDmk_EVEX 674
+KMOVDrk 675
+KMOVDrk_EVEX 676
+KMOVQkk 677
+KMOVQkk_EVEX 678
+KMOVQkm 679
+KMOVQkm_EVEX 680
+KMOVQkr 681
+KMOVQkr_EVEX 682
+KMOVQmk 683
+KMOVQmk_EVEX 684
+KMOVQrk 685
+KMOVQrk_EVEX 686
+KMOVWkk 687
+KMOVWkk_EVEX 688
+KMOVWkm 689
+KMOVWkm_EVEX 690
+KMOVWkr 691
+KMOVWkr_EVEX 692
+KMOVWmk 693
+KMOVWmk_EVEX 694
+KMOVWrk 695
+KMOVWrk_EVEX 696
+KNOTBkk 697
+KNOTDkk 698
+KNOTQkk 699
+KNOTWkk 700
+KORBkk 701
+KORDkk 702
+KORQkk 703
+KORTESTBkk 704
+KORTESTDkk 705
+KORTESTQkk 706
+KORTESTWkk 707
+KORWkk 708
+KSET 709
+KSHIFTLBki 710
+KSHIFTLDki 711
+KSHIFTLQki 712
+KSHIFTLWki 713
+KSHIFTRBki 714
+KSHIFTRDki 715
+KSHIFTRQki 716
+KSHIFTRWki 717
+KTESTBkk 718
+KTESTDkk 719
+KTESTQkk 720
+KTESTWkk 721
+KUNPCKBWkk 722
+KUNPCKDQkk 723
+KUNPCKWDkk 724
+KXNORBkk 725
+KXNORDkk 726
+KXNORQkk 727
+KXNORWkk 728
+KXORBkk 729
+KXORDkk 730
+KXORQkk 731
+KXORWkk 732
+LAHF 733
+LAR 734
+LCMPXCHG 735
+LDDQUrm 736
+LDMXCSR 737
+LDS 738
+LDTILECFG 739
+LDTILECFG_EVEX 740
+LD_F 741
+LD_Fp 742
+LD_Frr 743
+LEA 744
+LEAVE 745
+LES 746
+LFENCE 747
+LFS 748
+LGDT 749
+LGS 750
+LIDT 751
+LIFETIME_END 752
+LIFETIME_START 753
+LKGS 754
+LLDT 755
+LLWPCB 756
+LMSW 757
+LOADIWKEY 758
+LOAD_STACK_GUARD 759
+LOCAL_ESCAPE 760
+LOCK_ADD 761
+LOCK_AND 762
+LOCK_BTC 763
+LOCK_BTC_RM 764
+LOCK_BTR 765
+LOCK_BTR_RM 766
+LOCK_BTS 767
+LOCK_BTS_RM 768
+LOCK_DEC 769
+LOCK_INC 770
+LOCK_OR 771
+LOCK_PREFIX 772
+LOCK_SUB 773
+LOCK_XOR 774
+LODSB 775
+LODSL 776
+LODSQ 777
+LODSW 778
+LOOP 779
+LOOPE 780
+LOOPNE 781
+LRET 782
+LRETI 783
+LSL 784
+LSS 785
+LTRm 786
+LTRr 787
+LWPINS 788
+LWPVAL 789
+LXADD 790
+LZCNT 791
+MASKMOVDQU 792
+MASKPAIR 793
+MAXCPDrm 794
+MAXCPDrr 795
+MAXCPSrm 796
+MAXCPSrr 797
+MAXCSDrm 798
+MAXCSDrr 799
+MAXCSSrm 800
+MAXCSSrr 801
+MAXPDrm 802
+MAXPDrr 803
+MAXPSrm 804
+MAXPSrr 805
+MAXSDrm 806
+MAXSDrm_Int 807
+MAXSDrr 808
+MAXSDrr_Int 809
+MAXSSrm 810
+MAXSSrm_Int 811
+MAXSSrr 812
+MAXSSrr_Int 813
+MEMBARRIER 814
+MFENCE 815
+MINCPDrm 816
+MINCPDrr 817
+MINCPSrm 818
+MINCPSrr 819
+MINCSDrm 820
+MINCSDrr 821
+MINCSSrm 822
+MINCSSrr 823
+MINPDrm 824
+MINPDrr 825
+MINPSrm 826
+MINPSrr 827
+MINSDrm 828
+MINSDrm_Int 829
+MINSDrr 830
+MINSDrr_Int 831
+MINSSrm 832
+MINSSrm_Int 833
+MINSSrr 834
+MINSSrr_Int 835
+MMX_CVTPD 836
+MMX_CVTPI 837
+MMX_CVTPS 838
+MMX_CVTTPD 839
+MMX_CVTTPS 840
+MMX_EMMS 841
+MMX_MASKMOVQ 842
+MMX_MOVD 843
+MMX_MOVDQ 844
+MMX_MOVFR 845
+MMX_MOVNTQmr 846
+MMX_MOVQ 847
+MMX_PABSBrm 848
+MMX_PABSBrr 849
+MMX_PABSDrm 850
+MMX_PABSDrr 851
+MMX_PABSWrm 852
+MMX_PABSWrr 853
+MMX_PACKSSDWrm 854
+MMX_PACKSSDWrr 855
+MMX_PACKSSWBrm 856
+MMX_PACKSSWBrr 857
+MMX_PACKUSWBrm 858
+MMX_PACKUSWBrr 859
+MMX_PADDBrm 860
+MMX_PADDBrr 861
+MMX_PADDDrm 862
+MMX_PADDDrr 863
+MMX_PADDQrm 864
+MMX_PADDQrr 865
+MMX_PADDSBrm 866
+MMX_PADDSBrr 867
+MMX_PADDSWrm 868
+MMX_PADDSWrr 869
+MMX_PADDUSBrm 870
+MMX_PADDUSBrr 871
+MMX_PADDUSWrm 872
+MMX_PADDUSWrr 873
+MMX_PADDWrm 874
+MMX_PADDWrr 875
+MMX_PALIGNRrmi 876
+MMX_PALIGNRrri 877
+MMX_PANDNrm 878
+MMX_PANDNrr 879
+MMX_PANDrm 880
+MMX_PANDrr 881
+MMX_PAVGBrm 882
+MMX_PAVGBrr 883
+MMX_PAVGWrm 884
+MMX_PAVGWrr 885
+MMX_PCMPEQBrm 886
+MMX_PCMPEQBrr 887
+MMX_PCMPEQDrm 888
+MMX_PCMPEQDrr 889
+MMX_PCMPEQWrm 890
+MMX_PCMPEQWrr 891
+MMX_PCMPGTBrm 892
+MMX_PCMPGTBrr 893
+MMX_PCMPGTDrm 894
+MMX_PCMPGTDrr 895
+MMX_PCMPGTWrm 896
+MMX_PCMPGTWrr 897
+MMX_PEXTRWrri 898
+MMX_PHADDDrm 899
+MMX_PHADDDrr 900
+MMX_PHADDSWrm 901
+MMX_PHADDSWrr 902
+MMX_PHADDWrm 903
+MMX_PHADDWrr 904
+MMX_PHSUBDrm 905
+MMX_PHSUBDrr 906
+MMX_PHSUBSWrm 907
+MMX_PHSUBSWrr 908
+MMX_PHSUBWrm 909
+MMX_PHSUBWrr 910
+MMX_PINSRWrmi 911
+MMX_PINSRWrri 912
+MMX_PMADDUBSWrm 913
+MMX_PMADDUBSWrr 914
+MMX_PMADDWDrm 915
+MMX_PMADDWDrr 916
+MMX_PMAXSWrm 917
+MMX_PMAXSWrr 918
+MMX_PMAXUBrm 919
+MMX_PMAXUBrr 920
+MMX_PMINSWrm 921
+MMX_PMINSWrr 922
+MMX_PMINUBrm 923
+MMX_PMINUBrr 924
+MMX_PMOVMSKBrr 925
+MMX_PMULHRSWrm 926
+MMX_PMULHRSWrr 927
+MMX_PMULHUWrm 928
+MMX_PMULHUWrr 929
+MMX_PMULHWrm 930
+MMX_PMULHWrr 931
+MMX_PMULLWrm 932
+MMX_PMULLWrr 933
+MMX_PMULUDQrm 934
+MMX_PMULUDQrr 935
+MMX_PORrm 936
+MMX_PORrr 937
+MMX_PSADBWrm 938
+MMX_PSADBWrr 939
+MMX_PSHUFBrm 940
+MMX_PSHUFBrr 941
+MMX_PSHUFWmi 942
+MMX_PSHUFWri 943
+MMX_PSIGNBrm 944
+MMX_PSIGNBrr 945
+MMX_PSIGNDrm 946
+MMX_PSIGNDrr 947
+MMX_PSIGNWrm 948
+MMX_PSIGNWrr 949
+MMX_PSLLDri 950
+MMX_PSLLDrm 951
+MMX_PSLLDrr 952
+MMX_PSLLQri 953
+MMX_PSLLQrm 954
+MMX_PSLLQrr 955
+MMX_PSLLWri 956
+MMX_PSLLWrm 957
+MMX_PSLLWrr 958
+MMX_PSRADri 959
+MMX_PSRADrm 960
+MMX_PSRADrr 961
+MMX_PSRAWri 962
+MMX_PSRAWrm 963
+MMX_PSRAWrr 964
+MMX_PSRLDri 965
+MMX_PSRLDrm 966
+MMX_PSRLDrr 967
+MMX_PSRLQri 968
+MMX_PSRLQrm 969
+MMX_PSRLQrr 970
+MMX_PSRLWri 971
+MMX_PSRLWrm 972
+MMX_PSRLWrr 973
+MMX_PSUBBrm 974
+MMX_PSUBBrr 975
+MMX_PSUBDrm 976
+MMX_PSUBDrr 977
+MMX_PSUBQrm 978
+MMX_PSUBQrr 979
+MMX_PSUBSBrm 980
+MMX_PSUBSBrr 981
+MMX_PSUBSWrm 982
+MMX_PSUBSWrr 983
+MMX_PSUBUSBrm 984
+MMX_PSUBUSBrr 985
+MMX_PSUBUSWrm 986
+MMX_PSUBUSWrr 987
+MMX_PSUBWrm 988
+MMX_PSUBWrr 989
+MMX_PUNPCKHBWrm 990
+MMX_PUNPCKHBWrr 991
+MMX_PUNPCKHDQrm 992
+MMX_PUNPCKHDQrr 993
+MMX_PUNPCKHWDrm 994
+MMX_PUNPCKHWDrr 995
+MMX_PUNPCKLBWrm 996
+MMX_PUNPCKLBWrr 997
+MMX_PUNPCKLDQrm 998
+MMX_PUNPCKLDQrr 999
+MMX_PUNPCKLWDrm 1000
+MMX_PUNPCKLWDrr 1001
+MMX_PXORrm 1002
+MMX_PXORrr 1003
+MMX_SET 1004
+MONITOR 1005
+MONITORX 1006
+MONTMUL 1007
+MORESTACK_RET 1008
+MORESTACK_RET_RESTORE_R 1009
+MOV 1010
+MOVAPDmr 1011
+MOVAPDrm 1012
+MOVAPDrr 1013
+MOVAPDrr_REV 1014
+MOVAPSmr 1015
+MOVAPSrm 1016
+MOVAPSrr 1017
+MOVAPSrr_REV 1018
+MOVBE 1019
+MOVDDUPrm 1020
+MOVDDUPrr 1021
+MOVDI 1022
+MOVDIR 1023
+MOVDIRI 1024
+MOVDQAmr 1025
+MOVDQArm 1026
+MOVDQArr 1027
+MOVDQArr_REV 1028
+MOVDQUmr 1029
+MOVDQUrm 1030
+MOVDQUrr 1031
+MOVDQUrr_REV 1032
+MOVHLPSrr 1033
+MOVHPDmr 1034
+MOVHPDrm 1035
+MOVHPSmr 1036
+MOVHPSrm 1037
+MOVLHPSrr 1038
+MOVLPDmr 1039
+MOVLPDrm 1040
+MOVLPSmr 1041
+MOVLPSrm 1042
+MOVMSKPDrr 1043
+MOVMSKPSrr 1044
+MOVNTDQArm 1045
+MOVNTDQmr 1046
+MOVNTI 1047
+MOVNTImr 1048
+MOVNTPDmr 1049
+MOVNTPSmr 1050
+MOVNTSD 1051
+MOVNTSS 1052
+MOVPC 1053
+MOVPDI 1054
+MOVPQI 1055
+MOVPQIto 1056
+MOVQI 1057
+MOVRS 1058
+MOVSB 1059
+MOVSDmr 1060
+MOVSDrm 1061
+MOVSDrm_alt 1062
+MOVSDrr 1063
+MOVSDrr_REV 1064
+MOVSDto 1065
+MOVSHDUPrm 1066
+MOVSHDUPrr 1067
+MOVSHPmr 1068
+MOVSHPrm 1069
+MOVSL 1070
+MOVSLDUPrm 1071
+MOVSLDUPrr 1072
+MOVSQ 1073
+MOVSS 1074
+MOVSSmr 1075
+MOVSSrm 1076
+MOVSSrm_alt 1077
+MOVSSrr 1078
+MOVSSrr_REV 1079
+MOVSW 1080
+MOVSX 1081
+MOVUPDmr 1082
+MOVUPDrm 1083
+MOVUPDrr 1084
+MOVUPDrr_REV 1085
+MOVUPSmr 1086
+MOVUPSrm 1087
+MOVUPSrr 1088
+MOVUPSrr_REV 1089
+MOVZPQILo 1090
+MOVZX 1091
+MPSADBWrmi 1092
+MPSADBWrri 1093
+MUL 1094
+MULPDrm 1095
+MULPDrr 1096
+MULPSrm 1097
+MULPSrr 1098
+MULSDrm 1099
+MULSDrm_Int 1100
+MULSDrr 1101
+MULSDrr_Int 1102
+MULSSrm 1103
+MULSSrm_Int 1104
+MULSSrr 1105
+MULSSrr_Int 1106
+MULX 1107
+MUL_F 1108
+MUL_FI 1109
+MUL_FPrST 1110
+MUL_FST 1111
+MUL_Fp 1112
+MUL_FpI 1113
+MUL_FrST 1114
+MWAITX 1115
+MWAITX_SAVE_RBX 1116
+MWAITXrrr 1117
+MWAITrr 1118
+NEG 1119
+NOOP 1120
+NOOPL 1121
+NOOPLr 1122
+NOOPQ 1123
+NOOPQr 1124
+NOOPW 1125
+NOOPWr 1126
+NOT 1127
+OR 1128
+ORPDrm 1129
+ORPDrr 1130
+ORPSrm 1131
+ORPSrr 1132
+OUT 1133
+OUTSB 1134
+OUTSL 1135
+OUTSW 1136
+PABSBrm 1137
+PABSBrr 1138
+PABSDrm 1139
+PABSDrr 1140
+PABSWrm 1141
+PABSWrr 1142
+PACKSSDWrm 1143
+PACKSSDWrr 1144
+PACKSSWBrm 1145
+PACKSSWBrr 1146
+PACKUSDWrm 1147
+PACKUSDWrr 1148
+PACKUSWBrm 1149
+PACKUSWBrr 1150
+PADDBrm 1151
+PADDBrr 1152
+PADDDrm 1153
+PADDDrr 1154
+PADDQrm 1155
+PADDQrr 1156
+PADDSBrm 1157
+PADDSBrr 1158
+PADDSWrm 1159
+PADDSWrr 1160
+PADDUSBrm 1161
+PADDUSBrr 1162
+PADDUSWrm 1163
+PADDUSWrr 1164
+PADDWrm 1165
+PADDWrr 1166
+PALIGNRrmi 1167
+PALIGNRrri 1168
+PANDNrm 1169
+PANDNrr 1170
+PANDrm 1171
+PANDrr 1172
+PATCHABLE_EVENT_CALL 1173
+PATCHABLE_FUNCTION_ENTER 1174
+PATCHABLE_FUNCTION_EXIT 1175
+PATCHABLE_OP 1176
+PATCHABLE_RET 1177
+PATCHABLE_TAIL_CALL 1178
+PATCHABLE_TYPED_EVENT_CALL 1179
+PATCHPOINT 1180
+PAUSE 1181
+PAVGBrm 1182
+PAVGBrr 1183
+PAVGUSBrm 1184
+PAVGUSBrr 1185
+PAVGWrm 1186
+PAVGWrr 1187
+PBLENDVBrm 1188
+PBLENDVBrr 1189
+PBLENDWrmi 1190
+PBLENDWrri 1191
+PBNDKB 1192
+PCLMULQDQrmi 1193
+PCLMULQDQrri 1194
+PCMPEQBrm 1195
+PCMPEQBrr 1196
+PCMPEQDrm 1197
+PCMPEQDrr 1198
+PCMPEQQrm 1199
+PCMPEQQrr 1200
+PCMPEQWrm 1201
+PCMPEQWrr 1202
+PCMPESTRIrmi 1203
+PCMPESTRIrri 1204
+PCMPESTRMrmi 1205
+PCMPESTRMrri 1206
+PCMPGTBrm 1207
+PCMPGTBrr 1208
+PCMPGTDrm 1209
+PCMPGTDrr 1210
+PCMPGTQrm 1211
+PCMPGTQrr 1212
+PCMPGTWrm 1213
+PCMPGTWrr 1214
+PCMPISTRIrmi 1215
+PCMPISTRIrri 1216
+PCMPISTRMrmi 1217
+PCMPISTRMrri 1218
+PCONFIG 1219
+PDEP 1220
+PEXT 1221
+PEXTRBmri 1222
+PEXTRBrri 1223
+PEXTRDmri 1224
+PEXTRDrri 1225
+PEXTRQmri 1226
+PEXTRQrri 1227
+PEXTRWmri 1228
+PEXTRWrri 1229
+PEXTRWrri_REV 1230
+PF 1231
+PFACCrm 1232
+PFACCrr 1233
+PFADDrm 1234
+PFADDrr 1235
+PFCMPEQrm 1236
+PFCMPEQrr 1237
+PFCMPGErm 1238
+PFCMPGErr 1239
+PFCMPGTrm 1240
+PFCMPGTrr 1241
+PFMAXrm 1242
+PFMAXrr 1243
+PFMINrm 1244
+PFMINrr 1245
+PFMULrm 1246
+PFMULrr 1247
+PFNACCrm 1248
+PFNACCrr 1249
+PFPNACCrm 1250
+PFPNACCrr 1251
+PFRCPIT 1252
+PFRCPrm 1253
+PFRCPrr 1254
+PFRSQIT 1255
+PFRSQRTrm 1256
+PFRSQRTrr 1257
+PFSUBRrm 1258
+PFSUBRrr 1259
+PFSUBrm 1260
+PFSUBrr 1261
+PHADDDrm 1262
+PHADDDrr 1263
+PHADDSWrm 1264
+PHADDSWrr 1265
+PHADDWrm 1266
+PHADDWrr 1267
+PHI 1268
+PHMINPOSUWrm 1269
+PHMINPOSUWrr 1270
+PHSUBDrm 1271
+PHSUBDrr 1272
+PHSUBSWrm 1273
+PHSUBSWrr 1274
+PHSUBWrm 1275
+PHSUBWrr 1276
+PI 1277
+PINSRBrmi 1278
+PINSRBrri 1279
+PINSRDrmi 1280
+PINSRDrri 1281
+PINSRQrmi 1282
+PINSRQrri 1283
+PINSRWrmi 1284
+PINSRWrri 1285
+PLDTILECFGV 1286
+PLEA 1287
+PMADDUBSWrm 1288
+PMADDUBSWrr 1289
+PMADDWDrm 1290
+PMADDWDrr 1291
+PMAXSBrm 1292
+PMAXSBrr 1293
+PMAXSDrm 1294
+PMAXSDrr 1295
+PMAXSWrm 1296
+PMAXSWrr 1297
+PMAXUBrm 1298
+PMAXUBrr 1299
+PMAXUDrm 1300
+PMAXUDrr 1301
+PMAXUWrm 1302
+PMAXUWrr 1303
+PMINSBrm 1304
+PMINSBrr 1305
+PMINSDrm 1306
+PMINSDrr 1307
+PMINSWrm 1308
+PMINSWrr 1309
+PMINUBrm 1310
+PMINUBrr 1311
+PMINUDrm 1312
+PMINUDrr 1313
+PMINUWrm 1314
+PMINUWrr 1315
+PMOVMSKBrr 1316
+PMOVSXBDrm 1317
+PMOVSXBDrr 1318
+PMOVSXBQrm 1319
+PMOVSXBQrr 1320
+PMOVSXBWrm 1321
+PMOVSXBWrr 1322
+PMOVSXDQrm 1323
+PMOVSXDQrr 1324
+PMOVSXWDrm 1325
+PMOVSXWDrr 1326
+PMOVSXWQrm 1327
+PMOVSXWQrr 1328
+PMOVZXBDrm 1329
+PMOVZXBDrr 1330
+PMOVZXBQrm 1331
+PMOVZXBQrr 1332
+PMOVZXBWrm 1333
+PMOVZXBWrr 1334
+PMOVZXDQrm 1335
+PMOVZXDQrr 1336
+PMOVZXWDrm 1337
+PMOVZXWDrr 1338
+PMOVZXWQrm 1339
+PMOVZXWQrr 1340
+PMULDQrm 1341
+PMULDQrr 1342
+PMULHRSWrm 1343
+PMULHRSWrr 1344
+PMULHRWrm 1345
+PMULHRWrr 1346
+PMULHUWrm 1347
+PMULHUWrr 1348
+PMULHWrm 1349
+PMULHWrr 1350
+PMULLDrm 1351
+PMULLDrr 1352
+PMULLWrm 1353
+PMULLWrr 1354
+PMULUDQrm 1355
+PMULUDQrr 1356
+POP 1357
+POPA 1358
+POPCNT 1359
+POPDS 1360
+POPES 1361
+POPF 1362
+POPFS 1363
+POPGS 1364
+POPP 1365
+POPSS 1366
+PORrm 1367
+PORrr 1368
+PREALLOCATED_ARG 1369
+PREALLOCATED_SETUP 1370
+PREFETCH 1371
+PREFETCHIT 1372
+PREFETCHNTA 1373
+PREFETCHRST 1374
+PREFETCHT 1375
+PREFETCHW 1376
+PREFETCHWT 1377
+PROBED_ALLOCA 1378
+PSADBWrm 1379
+PSADBWrr 1380
+PSEUDO_PROBE 1381
+PSHUFBrm 1382
+PSHUFBrr 1383
+PSHUFDmi 1384
+PSHUFDri 1385
+PSHUFHWmi 1386
+PSHUFHWri 1387
+PSHUFLWmi 1388
+PSHUFLWri 1389
+PSIGNBrm 1390
+PSIGNBrr 1391
+PSIGNDrm 1392
+PSIGNDrr 1393
+PSIGNWrm 1394
+PSIGNWrr 1395
+PSLLDQri 1396
+PSLLDri 1397
+PSLLDrm 1398
+PSLLDrr 1399
+PSLLQri 1400
+PSLLQrm 1401
+PSLLQrr 1402
+PSLLWri 1403
+PSLLWrm 1404
+PSLLWrr 1405
+PSMASH 1406
+PSRADri 1407
+PSRADrm 1408
+PSRADrr 1409
+PSRAWri 1410
+PSRAWrm 1411
+PSRAWrr 1412
+PSRLDQri 1413
+PSRLDri 1414
+PSRLDrm 1415
+PSRLDrr 1416
+PSRLQri 1417
+PSRLQrm 1418
+PSRLQrr 1419
+PSRLWri 1420
+PSRLWrm 1421
+PSRLWrr 1422
+PSUBBrm 1423
+PSUBBrr 1424
+PSUBDrm 1425
+PSUBDrr 1426
+PSUBQrm 1427
+PSUBQrr 1428
+PSUBSBrm 1429
+PSUBSBrr 1430
+PSUBSWrm 1431
+PSUBSWrr 1432
+PSUBUSBrm 1433
+PSUBUSBrr 1434
+PSUBUSWrm 1435
+PSUBUSWrr 1436
+PSUBWrm 1437
+PSUBWrr 1438
+PSWAPDrm 1439
+PSWAPDrr 1440
+PT 1441
+PTCMMIMFP 1442
+PTCMMRLFP 1443
+PTCONJTCMMIMFP 1444
+PTCONJTFP 1445
+PTCVTROWD 1446
+PTCVTROWPS 1447
+PTDPBF 1448
+PTDPBHF 1449
+PTDPBSSD 1450
+PTDPBSSDV 1451
+PTDPBSUD 1452
+PTDPBSUDV 1453
+PTDPBUSD 1454
+PTDPBUSDV 1455
+PTDPBUUD 1456
+PTDPBUUDV 1457
+PTDPFP 1458
+PTDPHBF 1459
+PTDPHF 1460
+PTESTrm 1461
+PTESTrr 1462
+PTILELOADD 1463
+PTILELOADDRS 1464
+PTILELOADDRST 1465
+PTILELOADDRSV 1466
+PTILELOADDT 1467
+PTILELOADDV 1468
+PTILEMOVROWrre 1469
+PTILEMOVROWrreV 1470
+PTILEMOVROWrri 1471
+PTILEMOVROWrriV 1472
+PTILEPAIRLOAD 1473
+PTILEPAIRSTORE 1474
+PTILESTORED 1475
+PTILESTOREDV 1476
+PTILEZERO 1477
+PTILEZEROV 1478
+PTMMULTF 1479
+PTTCMMIMFP 1480
+PTTCMMRLFP 1481
+PTTDPBF 1482
+PTTDPFP 1483
+PTTMMULTF 1484
+PTTRANSPOSED 1485
+PTTRANSPOSEDV 1486
+PTWRITE 1487
+PTWRITEm 1488
+PTWRITEr 1489
+PUNPCKHBWrm 1490
+PUNPCKHBWrr 1491
+PUNPCKHDQrm 1492
+PUNPCKHDQrr 1493
+PUNPCKHQDQrm 1494
+PUNPCKHQDQrr 1495
+PUNPCKHWDrm 1496
+PUNPCKHWDrr 1497
+PUNPCKLBWrm 1498
+PUNPCKLBWrr 1499
+PUNPCKLDQrm 1500
+PUNPCKLDQrr 1501
+PUNPCKLQDQrm 1502
+PUNPCKLQDQrr 1503
+PUNPCKLWDrm 1504
+PUNPCKLWDrr 1505
+PUSH 1506
+PUSHA 1507
+PUSHCS 1508
+PUSHDS 1509
+PUSHES 1510
+PUSHF 1511
+PUSHFS 1512
+PUSHGS 1513
+PUSHP 1514
+PUSHSS 1515
+PVALIDATE 1516
+PXORrm 1517
+PXORrr 1518
+RCL 1519
+RCPPSm 1520
+RCPPSr 1521
+RCPSSm 1522
+RCPSSm_Int 1523
+RCPSSr 1524
+RCPSSr_Int 1525
+RCR 1526
+RDFLAGS 1527
+RDFSBASE 1528
+RDGSBASE 1529
+RDMSR 1530
+RDMSRLIST 1531
+RDMSRri 1532
+RDMSRri_EVEX 1533
+RDPID 1534
+RDPKRUr 1535
+RDPMC 1536
+RDPRU 1537
+RDRAND 1538
+RDSEED 1539
+RDSSPD 1540
+RDSSPQ 1541
+RDTSC 1542
+RDTSCP 1543
+REG_SEQUENCE 1544
+REPNE_PREFIX 1545
+REP_MOVSB 1546
+REP_MOVSD 1547
+REP_MOVSQ 1548
+REP_MOVSW 1549
+REP_PREFIX 1550
+REP_STOSB 1551
+REP_STOSD 1552
+REP_STOSQ 1553
+REP_STOSW 1554
+RET 1555
+RETI 1556
+REX 1557
+RMPADJUST 1558
+RMPQUERY 1559
+RMPUPDATE 1560
+ROL 1561
+ROR 1562
+RORX 1563
+ROUNDPDmi 1564
+ROUNDPDri 1565
+ROUNDPSmi 1566
+ROUNDPSri 1567
+ROUNDSDmi 1568
+ROUNDSDmi_Int 1569
+ROUNDSDri 1570
+ROUNDSDri_Int 1571
+ROUNDSSmi 1572
+ROUNDSSmi_Int 1573
+ROUNDSSri 1574
+ROUNDSSri_Int 1575
+RSM 1576
+RSQRTPSm 1577
+RSQRTPSr 1578
+RSQRTSSm 1579
+RSQRTSSm_Int 1580
+RSQRTSSr 1581
+RSQRTSSr_Int 1582
+RSTORSSP 1583
+SAHF 1584
+SALC 1585
+SAR 1586
+SARX 1587
+SAVEPREVSSP 1588
+SBB 1589
+SCASB 1590
+SCASL 1591
+SCASQ 1592
+SCASW 1593
+SEAMCALL 1594
+SEAMOPS 1595
+SEAMRET 1596
+SEG_ALLOCA 1597
+SEH_BeginEpilogue 1598
+SEH_EndEpilogue 1599
+SEH_EndPrologue 1600
+SEH_PushFrame 1601
+SEH_PushReg 1602
+SEH_SaveReg 1603
+SEH_SaveXMM 1604
+SEH_SetFrame 1605
+SEH_StackAlign 1606
+SEH_StackAlloc 1607
+SEH_UnwindV 1608
+SEH_UnwindVersion 1609
+SENDUIPI 1610
+SERIALIZE 1611
+SETB_C 1612
+SETCCm 1613
+SETCCm_EVEX 1614
+SETCCr 1615
+SETCCr_EVEX 1616
+SETSSBSY 1617
+SETZUCCm 1618
+SETZUCCr 1619
+SFENCE 1620
+SGDT 1621
+SHA 1622
+SHL 1623
+SHLD 1624
+SHLDROT 1625
+SHLX 1626
+SHR 1627
+SHRD 1628
+SHRDROT 1629
+SHRX 1630
+SHUFPDrmi 1631
+SHUFPDrri 1632
+SHUFPSrmi 1633
+SHUFPSrri 1634
+SIDT 1635
+SKINIT 1636
+SLDT 1637
+SLWPCB 1638
+SMSW 1639
+SQRTPDm 1640
+SQRTPDr 1641
+SQRTPSm 1642
+SQRTPSr 1643
+SQRTSDm 1644
+SQRTSDm_Int 1645
+SQRTSDr 1646
+SQRTSDr_Int 1647
+SQRTSSm 1648
+SQRTSSm_Int 1649
+SQRTSSr 1650
+SQRTSSr_Int 1651
+SQRT_F 1652
+SQRT_Fp 1653
+SS_PREFIX 1654
+STAC 1655
+STACKALLOC_W_PROBING 1656
+STACKMAP 1657
+STATEPOINT 1658
+STC 1659
+STD 1660
+STGI 1661
+STI 1662
+STMXCSR 1663
+STOSB 1664
+STOSL 1665
+STOSQ 1666
+STOSW 1667
+STR 1668
+STRm 1669
+STTILECFG 1670
+STTILECFG_EVEX 1671
+STUI 1672
+ST_F 1673
+ST_FP 1674
+ST_FPrr 1675
+ST_Fp 1676
+ST_FpP 1677
+ST_Frr 1678
+SUB 1679
+SUBPDrm 1680
+SUBPDrr 1681
+SUBPSrm 1682
+SUBPSrr 1683
+SUBREG_TO_REG 1684
+SUBR_F 1685
+SUBR_FI 1686
+SUBR_FPrST 1687
+SUBR_FST 1688
+SUBR_Fp 1689
+SUBR_FpI 1690
+SUBR_FrST 1691
+SUBSDrm 1692
+SUBSDrm_Int 1693
+SUBSDrr 1694
+SUBSDrr_Int 1695
+SUBSSrm 1696
+SUBSSrm_Int 1697
+SUBSSrr 1698
+SUBSSrr_Int 1699
+SUB_F 1700
+SUB_FI 1701
+SUB_FPrST 1702
+SUB_FST 1703
+SUB_Fp 1704
+SUB_FpI 1705
+SUB_FrST 1706
+SWAPGS 1707
+SYSCALL 1708
+SYSENTER 1709
+SYSEXIT 1710
+SYSRET 1711
+T 1712
+TAILJMPd 1713
+TAILJMPd_CC 1714
+TAILJMPm 1715
+TAILJMPr 1716
+TCMMIMFP 1717
+TCMMRLFP 1718
+TCONJTCMMIMFP 1719
+TCONJTFP 1720
+TCRETURN_HIPE 1721
+TCRETURN_WIN 1722
+TCRETURN_WINmi 1723
+TCRETURNdi 1724
+TCRETURNdicc 1725
+TCRETURNmi 1726
+TCRETURNri 1727
+TCVTROWD 1728
+TCVTROWPS 1729
+TDCALL 1730
+TDPBF 1731
+TDPBHF 1732
+TDPBSSD 1733
+TDPBSUD 1734
+TDPBUSD 1735
+TDPBUUD 1736
+TDPFP 1737
+TDPHBF 1738
+TDPHF 1739
+TEST 1740
+TESTUI 1741
+TILELOADD 1742
+TILELOADDRS 1743
+TILELOADDRST 1744
+TILELOADDRS_EVEX 1745
+TILELOADDT 1746
+TILELOADD_EVEX 1747
+TILEMOVROWrre 1748
+TILEMOVROWrri 1749
+TILERELEASE 1750
+TILESTORED 1751
+TILESTORED_EVEX 1752
+TILEZERO 1753
+TLBSYNC 1754
+TLSCall 1755
+TLS_addr 1756
+TLS_addrX 1757
+TLS_base_addr 1758
+TLS_base_addrX 1759
+TLS_desc 1760
+TMMULTF 1761
+TPAUSE 1762
+TRAP 1763
+TST_F 1764
+TST_Fp 1765
+TTCMMIMFP 1766
+TTCMMRLFP 1767
+TTDPBF 1768
+TTDPFP 1769
+TTMMULTF 1770
+TTRANSPOSED 1771
+TZCNT 1772
+TZMSK 1773
+UBSAN_UD 1774
+UCOMISDrm 1775
+UCOMISDrm_Int 1776
+UCOMISDrr 1777
+UCOMISDrr_Int 1778
+UCOMISSrm 1779
+UCOMISSrm_Int 1780
+UCOMISSrr 1781
+UCOMISSrr_Int 1782
+UCOM_FIPr 1783
+UCOM_FIr 1784
+UCOM_FPPr 1785
+UCOM_FPr 1786
+UCOM_FpIr 1787
+UCOM_Fpr 1788
+UCOM_Fr 1789
+UD 1790
+UIRET 1791
+UMONITOR 1792
+UMWAIT 1793
+UNPCKHPDrm 1794
+UNPCKHPDrr 1795
+UNPCKHPSrm 1796
+UNPCKHPSrr 1797
+UNPCKLPDrm 1798
+UNPCKLPDrr 1799
+UNPCKLPSrm 1800
+UNPCKLPSrr 1801
+URDMSRri 1802
+URDMSRri_EVEX 1803
+URDMSRrr 1804
+URDMSRrr_EVEX 1805
+UWRMSRir 1806
+UWRMSRir_EVEX 1807
+UWRMSRrr 1808
+UWRMSRrr_EVEX 1809
+V 1810
+VAARG 1811
+VAARG_X 1812
+VADDBF 1813
+VADDPDYrm 1814
+VADDPDYrr 1815
+VADDPDZ 1816
+VADDPDZrm 1817
+VADDPDZrmb 1818
+VADDPDZrmbk 1819
+VADDPDZrmbkz 1820
+VADDPDZrmk 1821
+VADDPDZrmkz 1822
+VADDPDZrr 1823
+VADDPDZrrb 1824
+VADDPDZrrbk 1825
+VADDPDZrrbkz 1826
+VADDPDZrrk 1827
+VADDPDZrrkz 1828
+VADDPDrm 1829
+VADDPDrr 1830
+VADDPHZ 1831
+VADDPHZrm 1832
+VADDPHZrmb 1833
+VADDPHZrmbk 1834
+VADDPHZrmbkz 1835
+VADDPHZrmk 1836
+VADDPHZrmkz 1837
+VADDPHZrr 1838
+VADDPHZrrb 1839
+VADDPHZrrbk 1840
+VADDPHZrrbkz 1841
+VADDPHZrrk 1842
+VADDPHZrrkz 1843
+VADDPSYrm 1844
+VADDPSYrr 1845
+VADDPSZ 1846
+VADDPSZrm 1847
+VADDPSZrmb 1848
+VADDPSZrmbk 1849
+VADDPSZrmbkz 1850
+VADDPSZrmk 1851
+VADDPSZrmkz 1852
+VADDPSZrr 1853
+VADDPSZrrb 1854
+VADDPSZrrbk 1855
+VADDPSZrrbkz 1856
+VADDPSZrrk 1857
+VADDPSZrrkz 1858
+VADDPSrm 1859
+VADDPSrr 1860
+VADDSDZrm 1861
+VADDSDZrm_Int 1862
+VADDSDZrmk_Int 1863
+VADDSDZrmkz_Int 1864
+VADDSDZrr 1865
+VADDSDZrr_Int 1866
+VADDSDZrrb_Int 1867
+VADDSDZrrbk_Int 1868
+VADDSDZrrbkz_Int 1869
+VADDSDZrrk_Int 1870
+VADDSDZrrkz_Int 1871
+VADDSDrm 1872
+VADDSDrm_Int 1873
+VADDSDrr 1874
+VADDSDrr_Int 1875
+VADDSHZrm 1876
+VADDSHZrm_Int 1877
+VADDSHZrmk_Int 1878
+VADDSHZrmkz_Int 1879
+VADDSHZrr 1880
+VADDSHZrr_Int 1881
+VADDSHZrrb_Int 1882
+VADDSHZrrbk_Int 1883
+VADDSHZrrbkz_Int 1884
+VADDSHZrrk_Int 1885
+VADDSHZrrkz_Int 1886
+VADDSSZrm 1887
+VADDSSZrm_Int 1888
+VADDSSZrmk_Int 1889
+VADDSSZrmkz_Int 1890
+VADDSSZrr 1891
+VADDSSZrr_Int 1892
+VADDSSZrrb_Int 1893
+VADDSSZrrbk_Int 1894
+VADDSSZrrbkz_Int 1895
+VADDSSZrrk_Int 1896
+VADDSSZrrkz_Int 1897
+VADDSSrm 1898
+VADDSSrm_Int 1899
+VADDSSrr 1900
+VADDSSrr_Int 1901
+VADDSUBPDYrm 1902
+VADDSUBPDYrr 1903
+VADDSUBPDrm 1904
+VADDSUBPDrr 1905
+VADDSUBPSYrm 1906
+VADDSUBPSYrr 1907
+VADDSUBPSrm 1908
+VADDSUBPSrr 1909
+VAESDECLASTYrm 1910
+VAESDECLASTYrr 1911
+VAESDECLASTZ 1912
+VAESDECLASTZrm 1913
+VAESDECLASTZrr 1914
+VAESDECLASTrm 1915
+VAESDECLASTrr 1916
+VAESDECYrm 1917
+VAESDECYrr 1918
+VAESDECZ 1919
+VAESDECZrm 1920
+VAESDECZrr 1921
+VAESDECrm 1922
+VAESDECrr 1923
+VAESENCLASTYrm 1924
+VAESENCLASTYrr 1925
+VAESENCLASTZ 1926
+VAESENCLASTZrm 1927
+VAESENCLASTZrr 1928
+VAESENCLASTrm 1929
+VAESENCLASTrr 1930
+VAESENCYrm 1931
+VAESENCYrr 1932
+VAESENCZ 1933
+VAESENCZrm 1934
+VAESENCZrr 1935
+VAESENCrm 1936
+VAESENCrr 1937
+VAESIMCrm 1938
+VAESIMCrr 1939
+VAESKEYGENASSISTrmi 1940
+VAESKEYGENASSISTrri 1941
+VALIGNDZ 1942
+VALIGNDZrmbi 1943
+VALIGNDZrmbik 1944
+VALIGNDZrmbikz 1945
+VALIGNDZrmi 1946
+VALIGNDZrmik 1947
+VALIGNDZrmikz 1948
+VALIGNDZrri 1949
+VALIGNDZrrik 1950
+VALIGNDZrrikz 1951
+VALIGNQZ 1952
+VALIGNQZrmbi 1953
+VALIGNQZrmbik 1954
+VALIGNQZrmbikz 1955
+VALIGNQZrmi 1956
+VALIGNQZrmik 1957
+VALIGNQZrmikz 1958
+VALIGNQZrri 1959
+VALIGNQZrrik 1960
+VALIGNQZrrikz 1961
+VANDNPDYrm 1962
+VANDNPDYrr 1963
+VANDNPDZ 1964
+VANDNPDZrm 1965
+VANDNPDZrmb 1966
+VANDNPDZrmbk 1967
+VANDNPDZrmbkz 1968
+VANDNPDZrmk 1969
+VANDNPDZrmkz 1970
+VANDNPDZrr 1971
+VANDNPDZrrk 1972
+VANDNPDZrrkz 1973
+VANDNPDrm 1974
+VANDNPDrr 1975
+VANDNPSYrm 1976
+VANDNPSYrr 1977
+VANDNPSZ 1978
+VANDNPSZrm 1979
+VANDNPSZrmb 1980
+VANDNPSZrmbk 1981
+VANDNPSZrmbkz 1982
+VANDNPSZrmk 1983
+VANDNPSZrmkz 1984
+VANDNPSZrr 1985
+VANDNPSZrrk 1986
+VANDNPSZrrkz 1987
+VANDNPSrm 1988
+VANDNPSrr 1989
+VANDPDYrm 1990
+VANDPDYrr 1991
+VANDPDZ 1992
+VANDPDZrm 1993
+VANDPDZrmb 1994
+VANDPDZrmbk 1995
+VANDPDZrmbkz 1996
+VANDPDZrmk 1997
+VANDPDZrmkz 1998
+VANDPDZrr 1999
+VANDPDZrrk 2000
+VANDPDZrrkz 2001
+VANDPDrm 2002
+VANDPDrr 2003
+VANDPSYrm 2004
+VANDPSYrr 2005
+VANDPSZ 2006
+VANDPSZrm 2007
+VANDPSZrmb 2008
+VANDPSZrmbk 2009
+VANDPSZrmbkz 2010
+VANDPSZrmk 2011
+VANDPSZrmkz 2012
+VANDPSZrr 2013
+VANDPSZrrk 2014
+VANDPSZrrkz 2015
+VANDPSrm 2016
+VANDPSrr 2017
+VASTART_SAVE_XMM_REGS 2018
+VBCSTNEBF 2019
+VBCSTNESH 2020
+VBLENDMPDZ 2021
+VBLENDMPDZrm 2022
+VBLENDMPDZrmb 2023
+VBLENDMPDZrmbk 2024
+VBLENDMPDZrmbkz 2025
+VBLENDMPDZrmk 2026
+VBLENDMPDZrmkz 2027
+VBLENDMPDZrr 2028
+VBLENDMPDZrrk 2029
+VBLENDMPDZrrkz 2030
+VBLENDMPSZ 2031
+VBLENDMPSZrm 2032
+VBLENDMPSZrmb 2033
+VBLENDMPSZrmbk 2034
+VBLENDMPSZrmbkz 2035
+VBLENDMPSZrmk 2036
+VBLENDMPSZrmkz 2037
+VBLENDMPSZrr 2038
+VBLENDMPSZrrk 2039
+VBLENDMPSZrrkz 2040
+VBLENDPDYrmi 2041
+VBLENDPDYrri 2042
+VBLENDPDrmi 2043
+VBLENDPDrri 2044
+VBLENDPSYrmi 2045
+VBLENDPSYrri 2046
+VBLENDPSrmi 2047
+VBLENDPSrri 2048
+VBLENDVPDYrmr 2049
+VBLENDVPDYrrr 2050
+VBLENDVPDrmr 2051
+VBLENDVPDrrr 2052
+VBLENDVPSYrmr 2053
+VBLENDVPSYrrr 2054
+VBLENDVPSrmr 2055
+VBLENDVPSrrr 2056
+VBROADCASTF 2057
+VBROADCASTI 2058
+VBROADCASTSDYrm 2059
+VBROADCASTSDYrr 2060
+VBROADCASTSDZ 2061
+VBROADCASTSDZrm 2062
+VBROADCASTSDZrmk 2063
+VBROADCASTSDZrmkz 2064
+VBROADCASTSDZrr 2065
+VBROADCASTSDZrrk 2066
+VBROADCASTSDZrrkz 2067
+VBROADCASTSSYrm 2068
+VBROADCASTSSYrr 2069
+VBROADCASTSSZ 2070
+VBROADCASTSSZrm 2071
+VBROADCASTSSZrmk 2072
+VBROADCASTSSZrmkz 2073
+VBROADCASTSSZrr 2074
+VBROADCASTSSZrrk 2075
+VBROADCASTSSZrrkz 2076
+VBROADCASTSSrm 2077
+VBROADCASTSSrr 2078
+VCMPBF 2079
+VCMPPDYrmi 2080
+VCMPPDYrri 2081
+VCMPPDZ 2082
+VCMPPDZrmbi 2083
+VCMPPDZrmbik 2084
+VCMPPDZrmi 2085
+VCMPPDZrmik 2086
+VCMPPDZrri 2087
+VCMPPDZrrib 2088
+VCMPPDZrribk 2089
+VCMPPDZrrik 2090
+VCMPPDrmi 2091
+VCMPPDrri 2092
+VCMPPHZ 2093
+VCMPPHZrmbi 2094
+VCMPPHZrmbik 2095
+VCMPPHZrmi 2096
+VCMPPHZrmik 2097
+VCMPPHZrri 2098
+VCMPPHZrrib 2099
+VCMPPHZrribk 2100
+VCMPPHZrrik 2101
+VCMPPSYrmi 2102
+VCMPPSYrri 2103
+VCMPPSZ 2104
+VCMPPSZrmbi 2105
+VCMPPSZrmbik 2106
+VCMPPSZrmi 2107
+VCMPPSZrmik 2108
+VCMPPSZrri 2109
+VCMPPSZrrib 2110
+VCMPPSZrribk 2111
+VCMPPSZrrik 2112
+VCMPPSrmi 2113
+VCMPPSrri 2114
+VCMPSDZrmi 2115
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+VREDUCESSZrrib 6286
+VREDUCESSZrribk 6287
+VREDUCESSZrribkz 6288
+VREDUCESSZrrik 6289
+VREDUCESSZrrikz 6290
+VRNDSCALEBF 6291
+VRNDSCALEPDZ 6292
+VRNDSCALEPDZrmbi 6293
+VRNDSCALEPDZrmbik 6294
+VRNDSCALEPDZrmbikz 6295
+VRNDSCALEPDZrmi 6296
+VRNDSCALEPDZrmik 6297
+VRNDSCALEPDZrmikz 6298
+VRNDSCALEPDZrri 6299
+VRNDSCALEPDZrrib 6300
+VRNDSCALEPDZrribk 6301
+VRNDSCALEPDZrribkz 6302
+VRNDSCALEPDZrrik 6303
+VRNDSCALEPDZrrikz 6304
+VRNDSCALEPHZ 6305
+VRNDSCALEPHZrmbi 6306
+VRNDSCALEPHZrmbik 6307
+VRNDSCALEPHZrmbikz 6308
+VRNDSCALEPHZrmi 6309
+VRNDSCALEPHZrmik 6310
+VRNDSCALEPHZrmikz 6311
+VRNDSCALEPHZrri 6312
+VRNDSCALEPHZrrib 6313
+VRNDSCALEPHZrribk 6314
+VRNDSCALEPHZrribkz 6315
+VRNDSCALEPHZrrik 6316
+VRNDSCALEPHZrrikz 6317
+VRNDSCALEPSZ 6318
+VRNDSCALEPSZrmbi 6319
+VRNDSCALEPSZrmbik 6320
+VRNDSCALEPSZrmbikz 6321
+VRNDSCALEPSZrmi 6322
+VRNDSCALEPSZrmik 6323
+VRNDSCALEPSZrmikz 6324
+VRNDSCALEPSZrri 6325
+VRNDSCALEPSZrrib 6326
+VRNDSCALEPSZrribk 6327
+VRNDSCALEPSZrribkz 6328
+VRNDSCALEPSZrrik 6329
+VRNDSCALEPSZrrikz 6330
+VRNDSCALESDZrmi 6331
+VRNDSCALESDZrmi_Int 6332
+VRNDSCALESDZrmik_Int 6333
+VRNDSCALESDZrmikz_Int 6334
+VRNDSCALESDZrri 6335
+VRNDSCALESDZrri_Int 6336
+VRNDSCALESDZrrib_Int 6337
+VRNDSCALESDZrribk_Int 6338
+VRNDSCALESDZrribkz_Int 6339
+VRNDSCALESDZrrik_Int 6340
+VRNDSCALESDZrrikz_Int 6341
+VRNDSCALESHZrmi 6342
+VRNDSCALESHZrmi_Int 6343
+VRNDSCALESHZrmik_Int 6344
+VRNDSCALESHZrmikz_Int 6345
+VRNDSCALESHZrri 6346
+VRNDSCALESHZrri_Int 6347
+VRNDSCALESHZrrib_Int 6348
+VRNDSCALESHZrribk_Int 6349
+VRNDSCALESHZrribkz_Int 6350
+VRNDSCALESHZrrik_Int 6351
+VRNDSCALESHZrrikz_Int 6352
+VRNDSCALESSZrmi 6353
+VRNDSCALESSZrmi_Int 6354
+VRNDSCALESSZrmik_Int 6355
+VRNDSCALESSZrmikz_Int 6356
+VRNDSCALESSZrri 6357
+VRNDSCALESSZrri_Int 6358
+VRNDSCALESSZrrib_Int 6359
+VRNDSCALESSZrribk_Int 6360
+VRNDSCALESSZrribkz_Int 6361
+VRNDSCALESSZrrik_Int 6362
+VRNDSCALESSZrrikz_Int 6363
+VROUNDPDYmi 6364
+VROUNDPDYri 6365
+VROUNDPDmi 6366
+VROUNDPDri 6367
+VROUNDPSYmi 6368
+VROUNDPSYri 6369
+VROUNDPSmi 6370
+VROUNDPSri 6371
+VROUNDSDmi 6372
+VROUNDSDmi_Int 6373
+VROUNDSDri 6374
+VROUNDSDri_Int 6375
+VROUNDSSmi 6376
+VROUNDSSmi_Int 6377
+VROUNDSSri 6378
+VROUNDSSri_Int 6379
+VRSQRT 6380
+VRSQRTBF 6381
+VRSQRTPHZ 6382
+VRSQRTPHZm 6383
+VRSQRTPHZmb 6384
+VRSQRTPHZmbk 6385
+VRSQRTPHZmbkz 6386
+VRSQRTPHZmk 6387
+VRSQRTPHZmkz 6388
+VRSQRTPHZr 6389
+VRSQRTPHZrk 6390
+VRSQRTPHZrkz 6391
+VRSQRTPSYm 6392
+VRSQRTPSYr 6393
+VRSQRTPSm 6394
+VRSQRTPSr 6395
+VRSQRTSHZrm 6396
+VRSQRTSHZrmk 6397
+VRSQRTSHZrmkz 6398
+VRSQRTSHZrr 6399
+VRSQRTSHZrrk 6400
+VRSQRTSHZrrkz 6401
+VRSQRTSSm 6402
+VRSQRTSSm_Int 6403
+VRSQRTSSr 6404
+VRSQRTSSr_Int 6405
+VSCALEFBF 6406
+VSCALEFPDZ 6407
+VSCALEFPDZrm 6408
+VSCALEFPDZrmb 6409
+VSCALEFPDZrmbk 6410
+VSCALEFPDZrmbkz 6411
+VSCALEFPDZrmk 6412
+VSCALEFPDZrmkz 6413
+VSCALEFPDZrr 6414
+VSCALEFPDZrrb 6415
+VSCALEFPDZrrbk 6416
+VSCALEFPDZrrbkz 6417
+VSCALEFPDZrrk 6418
+VSCALEFPDZrrkz 6419
+VSCALEFPHZ 6420
+VSCALEFPHZrm 6421
+VSCALEFPHZrmb 6422
+VSCALEFPHZrmbk 6423
+VSCALEFPHZrmbkz 6424
+VSCALEFPHZrmk 6425
+VSCALEFPHZrmkz 6426
+VSCALEFPHZrr 6427
+VSCALEFPHZrrb 6428
+VSCALEFPHZrrbk 6429
+VSCALEFPHZrrbkz 6430
+VSCALEFPHZrrk 6431
+VSCALEFPHZrrkz 6432
+VSCALEFPSZ 6433
+VSCALEFPSZrm 6434
+VSCALEFPSZrmb 6435
+VSCALEFPSZrmbk 6436
+VSCALEFPSZrmbkz 6437
+VSCALEFPSZrmk 6438
+VSCALEFPSZrmkz 6439
+VSCALEFPSZrr 6440
+VSCALEFPSZrrb 6441
+VSCALEFPSZrrbk 6442
+VSCALEFPSZrrbkz 6443
+VSCALEFPSZrrk 6444
+VSCALEFPSZrrkz 6445
+VSCALEFSDZrm 6446
+VSCALEFSDZrmk 6447
+VSCALEFSDZrmkz 6448
+VSCALEFSDZrr 6449
+VSCALEFSDZrrb_Int 6450
+VSCALEFSDZrrbk_Int 6451
+VSCALEFSDZrrbkz_Int 6452
+VSCALEFSDZrrk 6453
+VSCALEFSDZrrkz 6454
+VSCALEFSHZrm 6455
+VSCALEFSHZrmk 6456
+VSCALEFSHZrmkz 6457
+VSCALEFSHZrr 6458
+VSCALEFSHZrrb_Int 6459
+VSCALEFSHZrrbk_Int 6460
+VSCALEFSHZrrbkz_Int 6461
+VSCALEFSHZrrk 6462
+VSCALEFSHZrrkz 6463
+VSCALEFSSZrm 6464
+VSCALEFSSZrmk 6465
+VSCALEFSSZrmkz 6466
+VSCALEFSSZrr 6467
+VSCALEFSSZrrb_Int 6468
+VSCALEFSSZrrbk_Int 6469
+VSCALEFSSZrrbkz_Int 6470
+VSCALEFSSZrrk 6471
+VSCALEFSSZrrkz 6472
+VSCATTERDPDZ 6473
+VSCATTERDPDZmr 6474
+VSCATTERDPSZ 6475
+VSCATTERDPSZmr 6476
+VSCATTERPF 6477
+VSCATTERQPDZ 6478
+VSCATTERQPDZmr 6479
+VSCATTERQPSZ 6480
+VSCATTERQPSZmr 6481
+VSHA 6482
+VSHUFF 6483
+VSHUFI 6484
+VSHUFPDYrmi 6485
+VSHUFPDYrri 6486
+VSHUFPDZ 6487
+VSHUFPDZrmbi 6488
+VSHUFPDZrmbik 6489
+VSHUFPDZrmbikz 6490
+VSHUFPDZrmi 6491
+VSHUFPDZrmik 6492
+VSHUFPDZrmikz 6493
+VSHUFPDZrri 6494
+VSHUFPDZrrik 6495
+VSHUFPDZrrikz 6496
+VSHUFPDrmi 6497
+VSHUFPDrri 6498
+VSHUFPSYrmi 6499
+VSHUFPSYrri 6500
+VSHUFPSZ 6501
+VSHUFPSZrmbi 6502
+VSHUFPSZrmbik 6503
+VSHUFPSZrmbikz 6504
+VSHUFPSZrmi 6505
+VSHUFPSZrmik 6506
+VSHUFPSZrmikz 6507
+VSHUFPSZrri 6508
+VSHUFPSZrrik 6509
+VSHUFPSZrrikz 6510
+VSHUFPSrmi 6511
+VSHUFPSrri 6512
+VSM 6513
+VSQRTBF 6514
+VSQRTPDYm 6515
+VSQRTPDYr 6516
+VSQRTPDZ 6517
+VSQRTPDZm 6518
+VSQRTPDZmb 6519
+VSQRTPDZmbk 6520
+VSQRTPDZmbkz 6521
+VSQRTPDZmk 6522
+VSQRTPDZmkz 6523
+VSQRTPDZr 6524
+VSQRTPDZrb 6525
+VSQRTPDZrbk 6526
+VSQRTPDZrbkz 6527
+VSQRTPDZrk 6528
+VSQRTPDZrkz 6529
+VSQRTPDm 6530
+VSQRTPDr 6531
+VSQRTPHZ 6532
+VSQRTPHZm 6533
+VSQRTPHZmb 6534
+VSQRTPHZmbk 6535
+VSQRTPHZmbkz 6536
+VSQRTPHZmk 6537
+VSQRTPHZmkz 6538
+VSQRTPHZr 6539
+VSQRTPHZrb 6540
+VSQRTPHZrbk 6541
+VSQRTPHZrbkz 6542
+VSQRTPHZrk 6543
+VSQRTPHZrkz 6544
+VSQRTPSYm 6545
+VSQRTPSYr 6546
+VSQRTPSZ 6547
+VSQRTPSZm 6548
+VSQRTPSZmb 6549
+VSQRTPSZmbk 6550
+VSQRTPSZmbkz 6551
+VSQRTPSZmk 6552
+VSQRTPSZmkz 6553
+VSQRTPSZr 6554
+VSQRTPSZrb 6555
+VSQRTPSZrbk 6556
+VSQRTPSZrbkz 6557
+VSQRTPSZrk 6558
+VSQRTPSZrkz 6559
+VSQRTPSm 6560
+VSQRTPSr 6561
+VSQRTSDZm 6562
+VSQRTSDZm_Int 6563
+VSQRTSDZmk_Int 6564
+VSQRTSDZmkz_Int 6565
+VSQRTSDZr 6566
+VSQRTSDZr_Int 6567
+VSQRTSDZrb_Int 6568
+VSQRTSDZrbk_Int 6569
+VSQRTSDZrbkz_Int 6570
+VSQRTSDZrk_Int 6571
+VSQRTSDZrkz_Int 6572
+VSQRTSDm 6573
+VSQRTSDm_Int 6574
+VSQRTSDr 6575
+VSQRTSDr_Int 6576
+VSQRTSHZm 6577
+VSQRTSHZm_Int 6578
+VSQRTSHZmk_Int 6579
+VSQRTSHZmkz_Int 6580
+VSQRTSHZr 6581
+VSQRTSHZr_Int 6582
+VSQRTSHZrb_Int 6583
+VSQRTSHZrbk_Int 6584
+VSQRTSHZrbkz_Int 6585
+VSQRTSHZrk_Int 6586
+VSQRTSHZrkz_Int 6587
+VSQRTSSZm 6588
+VSQRTSSZm_Int 6589
+VSQRTSSZmk_Int 6590
+VSQRTSSZmkz_Int 6591
+VSQRTSSZr 6592
+VSQRTSSZr_Int 6593
+VSQRTSSZrb_Int 6594
+VSQRTSSZrbk_Int 6595
+VSQRTSSZrbkz_Int 6596
+VSQRTSSZrk_Int 6597
+VSQRTSSZrkz_Int 6598
+VSQRTSSm 6599
+VSQRTSSm_Int 6600
+VSQRTSSr 6601
+VSQRTSSr_Int 6602
+VSTMXCSR 6603
+VSUBBF 6604
+VSUBPDYrm 6605
+VSUBPDYrr 6606
+VSUBPDZ 6607
+VSUBPDZrm 6608
+VSUBPDZrmb 6609
+VSUBPDZrmbk 6610
+VSUBPDZrmbkz 6611
+VSUBPDZrmk 6612
+VSUBPDZrmkz 6613
+VSUBPDZrr 6614
+VSUBPDZrrb 6615
+VSUBPDZrrbk 6616
+VSUBPDZrrbkz 6617
+VSUBPDZrrk 6618
+VSUBPDZrrkz 6619
+VSUBPDrm 6620
+VSUBPDrr 6621
+VSUBPHZ 6622
+VSUBPHZrm 6623
+VSUBPHZrmb 6624
+VSUBPHZrmbk 6625
+VSUBPHZrmbkz 6626
+VSUBPHZrmk 6627
+VSUBPHZrmkz 6628
+VSUBPHZrr 6629
+VSUBPHZrrb 6630
+VSUBPHZrrbk 6631
+VSUBPHZrrbkz 6632
+VSUBPHZrrk 6633
+VSUBPHZrrkz 6634
+VSUBPSYrm 6635
+VSUBPSYrr 6636
+VSUBPSZ 6637
+VSUBPSZrm 6638
+VSUBPSZrmb 6639
+VSUBPSZrmbk 6640
+VSUBPSZrmbkz 6641
+VSUBPSZrmk 6642
+VSUBPSZrmkz 6643
+VSUBPSZrr 6644
+VSUBPSZrrb 6645
+VSUBPSZrrbk 6646
+VSUBPSZrrbkz 6647
+VSUBPSZrrk 6648
+VSUBPSZrrkz 6649
+VSUBPSrm 6650
+VSUBPSrr 6651
+VSUBSDZrm 6652
+VSUBSDZrm_Int 6653
+VSUBSDZrmk_Int 6654
+VSUBSDZrmkz_Int 6655
+VSUBSDZrr 6656
+VSUBSDZrr_Int 6657
+VSUBSDZrrb_Int 6658
+VSUBSDZrrbk_Int 6659
+VSUBSDZrrbkz_Int 6660
+VSUBSDZrrk_Int 6661
+VSUBSDZrrkz_Int 6662
+VSUBSDrm 6663
+VSUBSDrm_Int 6664
+VSUBSDrr 6665
+VSUBSDrr_Int 6666
+VSUBSHZrm 6667
+VSUBSHZrm_Int 6668
+VSUBSHZrmk_Int 6669
+VSUBSHZrmkz_Int 6670
+VSUBSHZrr 6671
+VSUBSHZrr_Int 6672
+VSUBSHZrrb_Int 6673
+VSUBSHZrrbk_Int 6674
+VSUBSHZrrbkz_Int 6675
+VSUBSHZrrk_Int 6676
+VSUBSHZrrkz_Int 6677
+VSUBSSZrm 6678
+VSUBSSZrm_Int 6679
+VSUBSSZrmk_Int 6680
+VSUBSSZrmkz_Int 6681
+VSUBSSZrr 6682
+VSUBSSZrr_Int 6683
+VSUBSSZrrb_Int 6684
+VSUBSSZrrbk_Int 6685
+VSUBSSZrrbkz_Int 6686
+VSUBSSZrrk_Int 6687
+VSUBSSZrrkz_Int 6688
+VSUBSSrm 6689
+VSUBSSrm_Int 6690
+VSUBSSrr 6691
+VSUBSSrr_Int 6692
+VTESTPDYrm 6693
+VTESTPDYrr 6694
+VTESTPDrm 6695
+VTESTPDrr 6696
+VTESTPSYrm 6697
+VTESTPSYrr 6698
+VTESTPSrm 6699
+VTESTPSrr 6700
+VUCOMISDZrm 6701
+VUCOMISDZrm_Int 6702
+VUCOMISDZrr 6703
+VUCOMISDZrr_Int 6704
+VUCOMISDZrrb 6705
+VUCOMISDrm 6706
+VUCOMISDrm_Int 6707
+VUCOMISDrr 6708
+VUCOMISDrr_Int 6709
+VUCOMISHZrm 6710
+VUCOMISHZrm_Int 6711
+VUCOMISHZrr 6712
+VUCOMISHZrr_Int 6713
+VUCOMISHZrrb 6714
+VUCOMISSZrm 6715
+VUCOMISSZrm_Int 6716
+VUCOMISSZrr 6717
+VUCOMISSZrr_Int 6718
+VUCOMISSZrrb 6719
+VUCOMISSrm 6720
+VUCOMISSrm_Int 6721
+VUCOMISSrr 6722
+VUCOMISSrr_Int 6723
+VUCOMXSDZrm 6724
+VUCOMXSDZrm_Int 6725
+VUCOMXSDZrr 6726
+VUCOMXSDZrr_Int 6727
+VUCOMXSDZrrb_Int 6728
+VUCOMXSHZrm 6729
+VUCOMXSHZrm_Int 6730
+VUCOMXSHZrr 6731
+VUCOMXSHZrr_Int 6732
+VUCOMXSHZrrb_Int 6733
+VUCOMXSSZrm 6734
+VUCOMXSSZrm_Int 6735
+VUCOMXSSZrr 6736
+VUCOMXSSZrr_Int 6737
+VUCOMXSSZrrb_Int 6738
+VUNPCKHPDYrm 6739
+VUNPCKHPDYrr 6740
+VUNPCKHPDZ 6741
+VUNPCKHPDZrm 6742
+VUNPCKHPDZrmb 6743
+VUNPCKHPDZrmbk 6744
+VUNPCKHPDZrmbkz 6745
+VUNPCKHPDZrmk 6746
+VUNPCKHPDZrmkz 6747
+VUNPCKHPDZrr 6748
+VUNPCKHPDZrrk 6749
+VUNPCKHPDZrrkz 6750
+VUNPCKHPDrm 6751
+VUNPCKHPDrr 6752
+VUNPCKHPSYrm 6753
+VUNPCKHPSYrr 6754
+VUNPCKHPSZ 6755
+VUNPCKHPSZrm 6756
+VUNPCKHPSZrmb 6757
+VUNPCKHPSZrmbk 6758
+VUNPCKHPSZrmbkz 6759
+VUNPCKHPSZrmk 6760
+VUNPCKHPSZrmkz 6761
+VUNPCKHPSZrr 6762
+VUNPCKHPSZrrk 6763
+VUNPCKHPSZrrkz 6764
+VUNPCKHPSrm 6765
+VUNPCKHPSrr 6766
+VUNPCKLPDYrm 6767
+VUNPCKLPDYrr 6768
+VUNPCKLPDZ 6769
+VUNPCKLPDZrm 6770
+VUNPCKLPDZrmb 6771
+VUNPCKLPDZrmbk 6772
+VUNPCKLPDZrmbkz 6773
+VUNPCKLPDZrmk 6774
+VUNPCKLPDZrmkz 6775
+VUNPCKLPDZrr 6776
+VUNPCKLPDZrrk 6777
+VUNPCKLPDZrrkz 6778
+VUNPCKLPDrm 6779
+VUNPCKLPDrr 6780
+VUNPCKLPSYrm 6781
+VUNPCKLPSYrr 6782
+VUNPCKLPSZ 6783
+VUNPCKLPSZrm 6784
+VUNPCKLPSZrmb 6785
+VUNPCKLPSZrmbk 6786
+VUNPCKLPSZrmbkz 6787
+VUNPCKLPSZrmk 6788
+VUNPCKLPSZrmkz 6789
+VUNPCKLPSZrr 6790
+VUNPCKLPSZrrk 6791
+VUNPCKLPSZrrkz 6792
+VUNPCKLPSrm 6793
+VUNPCKLPSrr 6794
+VXORPDYrm 6795
+VXORPDYrr 6796
+VXORPDZ 6797
+VXORPDZrm 6798
+VXORPDZrmb 6799
+VXORPDZrmbk 6800
+VXORPDZrmbkz 6801
+VXORPDZrmk 6802
+VXORPDZrmkz 6803
+VXORPDZrr 6804
+VXORPDZrrk 6805
+VXORPDZrrkz 6806
+VXORPDrm 6807
+VXORPDrr 6808
+VXORPSYrm 6809
+VXORPSYrr 6810
+VXORPSZ 6811
+VXORPSZrm 6812
+VXORPSZrmb 6813
+VXORPSZrmbk 6814
+VXORPSZrmbkz 6815
+VXORPSZrmk 6816
+VXORPSZrmkz 6817
+VXORPSZrr 6818
+VXORPSZrrk 6819
+VXORPSZrrkz 6820
+VXORPSrm 6821
+VXORPSrr 6822
+VZEROALL 6823
+VZEROUPPER 6824
+V_SET 6825
+V_SETALLONES 6826
+WAIT 6827
+WBINVD 6828
+WBNOINVD 6829
+WRFLAGS 6830
+WRFSBASE 6831
+WRGSBASE 6832
+WRMSR 6833
+WRMSRLIST 6834
+WRMSRNS 6835
+WRMSRNSir 6836
+WRMSRNSir_EVEX 6837
+WRPKRUr 6838
+WRSSD 6839
+WRSSD_EVEX 6840
+WRSSQ 6841
+WRSSQ_EVEX 6842
+WRUSSD 6843
+WRUSSD_EVEX 6844
+WRUSSQ 6845
+WRUSSQ_EVEX 6846
+XABORT 6847
+XABORT_DEF 6848
+XACQUIRE_PREFIX 6849
+XADD 6850
+XAM_F 6851
+XAM_Fp 6852
+XBEGIN 6853
+XCHG 6854
+XCH_F 6855
+XCRYPTCBC 6856
+XCRYPTCFB 6857
+XCRYPTCTR 6858
+XCRYPTECB 6859
+XCRYPTOFB 6860
+XEND 6861
+XGETBV 6862
+XLAT 6863
+XOR 6864
+XORPDrm 6865
+XORPDrr 6866
+XORPSrm 6867
+XORPSrr 6868
+XRELEASE_PREFIX 6869
+XRESLDTRK 6870
+XRSTOR 6871
+XRSTORS 6872
+XSAVE 6873
+XSAVEC 6874
+XSAVEOPT 6875
+XSAVES 6876
+XSETBV 6877
+XSHA 6878
+XSTORE 6879
+XSUSLDTRK 6880
+XTEST 6881
+Immediate 6882
+CImmediate 6883
+FPImmediate 6884
+MBB 6885
+FrameIndex 6886
+ConstantPoolIndex 6887
+TargetIndex 6888
+JumpTableIndex 6889
+ExternalSymbol 6890
+GlobalAddress 6891
+BlockAddress 6892
+RegisterMask 6893
+RegisterLiveOut 6894
+Metadata 6895
+MCSymbol 6896
+CFIIndex 6897
+IntrinsicID 6898
+Predicate 6899
+ShuffleMask 6900
+PhyReg_GR8 6901
+PhyReg_GRH8 6902
+PhyReg_GR8_NOREX2 6903
+PhyReg_GR8_NOREX 6904
+PhyReg_GR8_ABCD_H 6905
+PhyReg_GR8_ABCD_L 6906
+PhyReg_GRH16 6907
+PhyReg_GR16 6908
+PhyReg_GR16_NOREX2 6909
+PhyReg_GR16_NOREX 6910
+PhyReg_VK1 6911
+PhyReg_VK16 6912
+PhyReg_VK2 6913
+PhyReg_VK4 6914
+PhyReg_VK8 6915
+PhyReg_VK16WM 6916
+PhyReg_VK1WM 6917
+PhyReg_VK2WM 6918
+PhyReg_VK4WM 6919
+PhyReg_VK8WM 6920
+PhyReg_SEGMENT_REG 6921
+PhyReg_GR16_ABCD 6922
+PhyReg_FPCCR 6923
+PhyReg_FR16X 6924
+PhyReg_FR16 6925
+PhyReg_VK16PAIR 6926
+PhyReg_VK1PAIR 6927
+PhyReg_VK2PAIR 6928
+PhyReg_VK4PAIR 6929
+PhyReg_VK8PAIR 6930
+PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6931
+PhyReg_LOW32_ADDR_ACCESS_RBP 6932
+PhyReg_LOW32_ADDR_ACCESS 6933
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6934
+PhyReg_FR32X 6935
+PhyReg_GR32 6936
+PhyReg_GR32_NOSP 6937
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6938
+PhyReg_DEBUG_REG 6939
+PhyReg_FR32 6940
+PhyReg_GR32_NOREX2 6941
+PhyReg_GR32_NOREX2_NOSP 6942
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6943
+PhyReg_GR32_NOREX 6944
+PhyReg_VK32 6945
+PhyReg_GR32_NOREX_NOSP 6946
+PhyReg_RFP32 6947
+PhyReg_VK32WM 6948
+PhyReg_GR32_ABCD 6949
+PhyReg_GR32_TC 6950
+PhyReg_GR32_ABCD_and_GR32_TC 6951
+PhyReg_GR32_AD 6952
+PhyReg_GR32_ArgRef 6953
+PhyReg_GR32_BPSP 6954
+PhyReg_GR32_BSI 6955
+PhyReg_GR32_CB 6956
+PhyReg_GR32_DC 6957
+PhyReg_GR32_DIBP 6958
+PhyReg_GR32_SIDI 6959
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6960
+PhyReg_CCR 6961
+PhyReg_DFCCR 6962
+PhyReg_GR32_ABCD_and_GR32_BSI 6963
+PhyReg_GR32_AD_and_GR32_ArgRef 6964
+PhyReg_GR32_ArgRef_and_GR32_CB 6965
+PhyReg_GR32_BPSP_and_GR32_DIBP 6966
+PhyReg_GR32_BPSP_and_GR32_TC 6967
+PhyReg_GR32_BSI_and_GR32_SIDI 6968
+PhyReg_GR32_DIBP_and_GR32_SIDI 6969
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6970
+PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6971
+PhyReg_RFP64 6972
+PhyReg_GR64 6973
+PhyReg_FR64X 6974
+PhyReg_GR64_with_sub_8bit 6975
+PhyReg_GR64_NOSP 6976
+PhyReg_GR64_NOREX2 6977
+PhyReg_CONTROL_REG 6978
+PhyReg_FR64 6979
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6980
+PhyReg_GR64_NOREX2_NOSP 6981
+PhyReg_GR64PLTSafe 6982
+PhyReg_GR64_TC 6983
+PhyReg_GR64_NOREX 6984
+PhyReg_GR64_TCW64 6985
+PhyReg_GR64_TC_with_sub_8bit 6986
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6987
+PhyReg_GR64_TCW64_with_sub_8bit 6988
+PhyReg_GR64_TC_and_GR64_TCW64 6989
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6990
+PhyReg_VK64 6991
+PhyReg_VR64 6992
+PhyReg_GR64PLTSafe_and_GR64_TC 6993
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6994
+PhyReg_GR64_NOREX_NOSP 6995
+PhyReg_GR64_NOREX_and_GR64_TC 6996
+PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6997
+PhyReg_VK64WM 6998
+PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6999
+PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7000
+PhyReg_GR64PLTSafe_and_GR64_TCW64 7001
+PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7002
+PhyReg_GR64_NOREX_and_GR64_TCW64 7003
+PhyReg_GR64_ABCD 7004
+PhyReg_GR64_with_sub_32bit_in_GR32_TC 7005
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7006
+PhyReg_GR64_AD 7007
+PhyReg_GR64_ArgRef 7008
+PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7009
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 7010
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 7011
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI 7012
+PhyReg_GR64_with_sub_32bit_in_GR32_CB 7013
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 7014
+PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 7015
+PhyReg_GR64_A 7016
+PhyReg_GR64_ArgRef_and_GR64_TC 7017
+PhyReg_GR64_and_LOW32_ADDR_ACCESS 7018
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7019
+PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7020
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7021
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7022
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7023
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7024
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7025
+PhyReg_RST 7026
+PhyReg_RFP80 7027
+PhyReg_RFP80_7 7028
+PhyReg_VR128X 7029
+PhyReg_VR128 7030
+PhyReg_VR256X 7031
+PhyReg_VR256 7032
+PhyReg_VR512 7033
+PhyReg_VR512_0_15 7034
+PhyReg_TILE 7035
+PhyReg_TILEPAIR 7036
+VirtReg_GR8 7037
+VirtReg_GRH8 7038
+VirtReg_GR8_NOREX2 7039
+VirtReg_GR8_NOREX 7040
+VirtReg_GR8_ABCD_H 7041
+VirtReg_GR8_ABCD_L 7042
+VirtReg_GRH16 7043
+VirtReg_GR16 7044
+VirtReg_GR16_NOREX2 7045
+VirtReg_GR16_NOREX 7046
+VirtReg_VK1 7047
+VirtReg_VK16 7048
+VirtReg_VK2 7049
+VirtReg_VK4 7050
+VirtReg_VK8 7051
+VirtReg_VK16WM 7052
+VirtReg_VK1WM 7053
+VirtReg_VK2WM 7054
+VirtReg_VK4WM 7055
+VirtReg_VK8WM 7056
+VirtReg_SEGMENT_REG 7057
+VirtReg_GR16_ABCD 7058
+VirtReg_FPCCR 7059
+VirtReg_FR16X 7060
+VirtReg_FR16 7061
+VirtReg_VK16PAIR 7062
+VirtReg_VK1PAIR 7063
+VirtReg_VK2PAIR 7064
+VirtReg_VK4PAIR 7065
+VirtReg_VK8PAIR 7066
+VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7067
+VirtReg_LOW32_ADDR_ACCESS_RBP 7068
+VirtReg_LOW32_ADDR_ACCESS 7069
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7070
+VirtReg_FR32X 7071
+VirtReg_GR32 7072
+VirtReg_GR32_NOSP 7073
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7074
+VirtReg_DEBUG_REG 7075
+VirtReg_FR32 7076
+VirtReg_GR32_NOREX2 7077
+VirtReg_GR32_NOREX2_NOSP 7078
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7079
+VirtReg_GR32_NOREX 7080
+VirtReg_VK32 7081
+VirtReg_GR32_NOREX_NOSP 7082
+VirtReg_RFP32 7083
+VirtReg_VK32WM 7084
+VirtReg_GR32_ABCD 7085
+VirtReg_GR32_TC 7086
+VirtReg_GR32_ABCD_and_GR32_TC 7087
+VirtReg_GR32_AD 7088
+VirtReg_GR32_ArgRef 7089
+VirtReg_GR32_BPSP 7090
+VirtReg_GR32_BSI 7091
+VirtReg_GR32_CB 7092
+VirtReg_GR32_DC 7093
+VirtReg_GR32_DIBP 7094
+VirtReg_GR32_SIDI 7095
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7096
+VirtReg_CCR 7097
+VirtReg_DFCCR 7098
+VirtReg_GR32_ABCD_and_GR32_BSI 7099
+VirtReg_GR32_AD_and_GR32_ArgRef 7100
+VirtReg_GR32_ArgRef_and_GR32_CB 7101
+VirtReg_GR32_BPSP_and_GR32_DIBP 7102
+VirtReg_GR32_BPSP_and_GR32_TC 7103
+VirtReg_GR32_BSI_and_GR32_SIDI 7104
+VirtReg_GR32_DIBP_and_GR32_SIDI 7105
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7106
+VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7107
+VirtReg_RFP64 7108
+VirtReg_GR64 7109
+VirtReg_FR64X 7110
+VirtReg_GR64_with_sub_8bit 7111
+VirtReg_GR64_NOSP 7112
+VirtReg_GR64_NOREX2 7113
+VirtReg_CONTROL_REG 7114
+VirtReg_FR64 7115
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7116
+VirtReg_GR64_NOREX2_NOSP 7117
+VirtReg_GR64PLTSafe 7118
+VirtReg_GR64_TC 7119
+VirtReg_GR64_NOREX 7120
+VirtReg_GR64_TCW64 7121
+VirtReg_GR64_TC_with_sub_8bit 7122
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7123
+VirtReg_GR64_TCW64_with_sub_8bit 7124
+VirtReg_GR64_TC_and_GR64_TCW64 7125
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7126
+VirtReg_VK64 7127
+VirtReg_VR64 7128
+VirtReg_GR64PLTSafe_and_GR64_TC 7129
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7130
+VirtReg_GR64_NOREX_NOSP 7131
+VirtReg_GR64_NOREX_and_GR64_TC 7132
+VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7133
+VirtReg_VK64WM 7134
+VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7135
+VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7136
+VirtReg_GR64PLTSafe_and_GR64_TCW64 7137
+VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7138
+VirtReg_GR64_NOREX_and_GR64_TCW64 7139
+VirtReg_GR64_ABCD 7140
+VirtReg_GR64_with_sub_32bit_in_GR32_TC 7141
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7142
+VirtReg_GR64_AD 7143
+VirtReg_GR64_ArgRef 7144
+VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7145
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7146
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7147
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7148
+VirtReg_GR64_with_sub_32bit_in_GR32_CB 7149
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7150
+VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7151
+VirtReg_GR64_A 7152
+VirtReg_GR64_ArgRef_and_GR64_TC 7153
+VirtReg_GR64_and_LOW32_ADDR_ACCESS 7154
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7155
+VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7156
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7157
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7158
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7159
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7160
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7161
+VirtReg_RST 7162
+VirtReg_RFP80 7163
+VirtReg_RFP80_7 7164
+VirtReg_VR128X 7165
+VirtReg_VR128 7166
+VirtReg_VR256X 7167
+VirtReg_VR256 7168
+VirtReg_VR512 7169
+VirtReg_VR512_0_15 7170
+VirtReg_TILE 7171
+VirtReg_TILEPAIR 7172
diff --git a/llvm/test/tools/llvm-ir2vec/triplets.mir b/llvm/test/tools/llvm-ir2vec/triplets.mir
new file mode 100644
index 0000000000000..274984ae9e91d
--- /dev/null
+++ b/llvm/test/tools/llvm-ir2vec/triplets.mir
@@ -0,0 +1,61 @@
+# REQUIRES: x86_64-linux
+# RUN: llvm-ir2vec triplets --mode=mir %s -o 2>&1 %t1.log
+# RUN:
diff %S/output/reference_triplets.txt %t1.log
+
+--- |
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-unknown-linux-gnu"
+
+ define dso_local noundef i32 @add_function(i32 noundef %a, i32 noundef %b) {
+ entry:
+ %sum = add nsw i32 %a, %b
+ ret i32 %sum
+ }
+
+ define dso_local noundef i32 @mul_function(i32 noundef %x, i32 noundef %y) {
+ entry:
+ %product = mul nsw i32 %x, %y
+ ret i32 %product
+ }
+...
+---
+name: add_function
+alignment: 16
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr32 }
+ - { id: 2, class: gr32 }
+liveins:
+ - { reg: '$edi', virtual-reg: '%0' }
+ - { reg: '$esi', virtual-reg: '%1' }
+body: |
+ bb.0.entry:
+ liveins: $edi, $esi
+
+ %1:gr32 = COPY $esi
+ %0:gr32 = COPY $edi
+ %2:gr32 = nsw ADD32rr %0, %1, implicit-def dead $eflags
+ $eax = COPY %2
+ RET 0, $eax
+
+---
+name: mul_function
+alignment: 16
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+ - { id: 1, class: gr32 }
+ - { id: 2, class: gr32 }
+liveins:
+ - { reg: '$edi', virtual-reg: '%0' }
+ - { reg: '$esi', virtual-reg: '%1' }
+body: |
+ bb.0.entry:
+ liveins: $edi, $esi
+
+ %1:gr32 = COPY $esi
+ %0:gr32 = COPY $edi
+ %2:gr32 = nsw IMUL32rr %0, %1, implicit-def dead $eflags
+ $eax = COPY %2
+ RET 0, $eax
diff --git a/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp b/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
index a723d379129e6..7402782bfd404 100644
--- a/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
+++ b/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
@@ -19,12 +19,22 @@
/// Generates numeric triplets (head, tail, relation) for vocabulary
/// training. Output format: MAX_RELATION=N header followed by
/// head\ttail\trelation lines. Relations: 0=Type, 1=Next, 2+=Arg0,Arg1,...
-/// Usage: llvm-ir2vec triplets input.bc -o train2id.txt
+///
+/// For LLVM IR:
+/// llvm-ir2vec triplets input.bc -o train2id.txt
+///
+/// For Machine IR:
+/// llvm-ir2vec triplets -mode=mir input.mir -o train2id.txt
///
/// 2. Entity Mappings (entities):
/// Generates entity mappings for vocabulary training.
/// Output format: <total_entities> header followed by entity\tid lines.
-/// Usage: llvm-ir2vec entities input.bc -o entity2id.txt
+///
+/// For LLVM IR:
+/// llvm-ir2vec entities input.bc -o entity2id.txt
+///
+/// For Machine IR:
+/// llvm-ir2vec entities -mode=mir input.mir -o entity2id.txt
///
/// 3. Embedding Generation (embeddings):
/// Generates IR2Vec/MIR2Vec embeddings using a trained vocabulary.
@@ -67,6 +77,8 @@
#include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/WithColor.h"
@@ -106,11 +118,10 @@ static cl::SubCommand
"Generate embeddings using trained vocabulary");
// Common options
-static cl::opt<std::string>
- InputFilename(cl::Positional,
- cl::desc("<input bitcode file or '-' for stdin>"),
- cl::init("-"), cl::sub(TripletsSubCmd),
- cl::sub(EmbeddingsSubCmd), cl::cat(CommonCategory));
+static cl::opt<std::string> InputFilename(
+ cl::Positional, cl::desc("<input bitcode/MIR file or '-' for stdin>"),
+ cl::init("-"), cl::sub(TripletsSubCmd), cl::sub(EntitiesSubCmd),
+ cl::sub(EmbeddingsSubCmd), cl::cat(CommonCategory));
static cl::opt<std::string> OutputFilename("o", cl::desc("Output filename"),
cl::value_desc("filename"),
@@ -345,6 +356,12 @@ Error processModule(Module &M, raw_ostream &OS) {
namespace mir2vec {
+/// Relation types for MIR2Vec triplet generation
+enum MIRRelationType {
+ MIRNextRelation = 0, ///< Sequential instruction relationship
+ MIRArgRelation = 1 ///< Instruction to operand relationship (ArgRelation + N)
+};
+
/// Helper class for MIR2Vec embedding generation
class MIR2VecTool {
private:
@@ -354,7 +371,7 @@ class MIR2VecTool {
public:
explicit MIR2VecTool(MachineModuleInfo &MMI) : MMI(MMI) {}
- /// Initialize MIR2Vec vocabulary
+ /// Initialize MIR2Vec vocabulary from file (for embeddings generation)
bool initializeVocabulary(const Module &M) {
MIR2VecVocabProvider Provider(MMI);
auto VocabOrErr = Provider.getVocabulary(M);
@@ -368,6 +385,146 @@ class MIR2VecTool {
return true;
}
+ /// Initialize vocabulary with layout information only.
+ /// This creates a minimal vocabulary with correct layout but no actual
+ /// embeddings. Sufficient for generating training data and entity mappings.
+ ///
+ /// Note: Requires target-specific information from the first machine function
+ /// to determine the vocabulary layout (number of opcodes, register classes).
+ ///
+ /// FIXME: Use --target option to get target info directly, avoiding the need
+ /// to parse machine functions for pre-training operations.
+ bool initializeVocabularyForLayout(const Module &M) {
+ for (const Function &F : M) {
+ if (F.isDeclaration())
+ continue;
+
+ MachineFunction *MF = MMI.getMachineFunction(F);
+ if (!MF)
+ continue;
+
+ const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
+ const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
+
+ auto VocabOrErr =
+ MIRVocabulary::createDummyVocabForTest(TII, TRI, MRI, 1);
+ if (!VocabOrErr) {
+ WithColor::error(errs(), ToolName)
+ << "Failed to create dummy vocabulary - "
+ << toString(VocabOrErr.takeError()) << "\n";
+ return false;
+ }
+ Vocab = std::make_unique<MIRVocabulary>(std::move(*VocabOrErr));
+ return true;
+ }
+
+ WithColor::error(errs(), ToolName)
+ << "No machine functions found to initialize vocabulary\n";
+ return false;
+ }
+
+ /// Generate triplets for the module
+ /// Output format: MAX_RELATION=N header followed by relationships
+ void generateTriplets(const Module &M, raw_ostream &OS) const {
+ unsigned MaxRelation = MIRNextRelation; // Track maximum relation ID
+ std::string Relationships;
+ raw_string_ostream RelOS(Relationships);
+
+ for (const Function &F : M) {
+ if (F.isDeclaration())
+ continue;
+
+ MachineFunction *MF = MMI.getMachineFunction(F);
+ if (!MF) {
+ WithColor::warning(errs(), ToolName)
+ << "No MachineFunction for " << F.getName() << "\n";
+ continue;
+ }
+
+ unsigned FuncMaxRelation = generateTriplets(*MF, RelOS);
+ MaxRelation = std::max(MaxRelation, FuncMaxRelation);
+ }
+
+ RelOS.flush();
+
+ // Write metadata header followed by relationships
+ OS << "MAX_RELATION=" << MaxRelation << '\n';
+ OS << Relationships;
+ }
+
+ /// Generate triplets for a single machine function
+ /// Returns the maximum relation ID used in this function
+ unsigned generateTriplets(const MachineFunction &MF, raw_ostream &OS) const {
+ unsigned MaxRelation = MIRNextRelation;
+ unsigned PrevOpcode = 0;
+ bool HasPrevOpcode = false;
+
+ if (!Vocab) {
+ WithColor::error(errs(), ToolName)
+ << "MIR Vocabulary must be initialized for triplet generation.\n";
+ return MaxRelation;
+ }
+
+ for (const MachineBasicBlock &MBB : MF) {
+ for (const MachineInstr &MI : MBB) {
+ // Skip debug instructions
+ if (MI.isDebugInstr())
+ continue;
+
+ // Get opcode entity ID
+ unsigned OpcodeID = Vocab->getEntityIDForOpcode(MI.getOpcode());
+
+ // Add "Next" relationship with previous instruction
+ if (HasPrevOpcode) {
+ OS << PrevOpcode << '\t' << OpcodeID << '\t' << MIRNextRelation
+ << '\n';
+ LLVM_DEBUG(dbgs()
+ << Vocab->getStringKey(PrevOpcode) << '\t'
+ << Vocab->getStringKey(OpcodeID) << '\t' << "Next\n");
+ }
+
+ // Add "Arg" relationships for operands
+ unsigned ArgIndex = 0;
+ for (const MachineOperand &MO : MI.operands()) {
+ auto OperandID = Vocab->getEntityIDForMachineOperand(MO);
+ unsigned RelationID = MIRArgRelation + ArgIndex;
+ OS << OpcodeID << '\t' << OperandID << '\t' << RelationID << '\n';
+ LLVM_DEBUG({
+ std::string OperandStr = Vocab->getStringKey(OperandID);
+ dbgs() << Vocab->getStringKey(OpcodeID) << '\t' << OperandStr
+ << '\t' << "Arg" << ArgIndex << '\n';
+ });
+
+ ++ArgIndex;
+ }
+
+ // Update MaxRelation if there were operands
+ if (ArgIndex > 0)
+ MaxRelation = std::max(MaxRelation, MIRArgRelation + ArgIndex - 1);
+
+ PrevOpcode = OpcodeID;
+ HasPrevOpcode = true;
+ }
+ }
+
+ return MaxRelation;
+ }
+
+ /// Generate entity mappings with vocabulary
+ void generateEntityMappings(raw_ostream &OS) const {
+ if (!Vocab) {
+ WithColor::error(errs(), ToolName)
+ << "Vocabulary must be initialized for entity mappings.\n";
+ return;
+ }
+
+ const unsigned EntityCount = Vocab->getCanonicalSize();
+ OS << EntityCount << "\n";
+ for (unsigned EntityID = 0; EntityID < EntityCount; ++EntityID)
+ OS << Vocab->getStringKey(EntityID) << '\t' << EntityID << '\n';
+ }
+
/// Generate embeddings for all machine functions in the module
void generateEmbeddings(const Module &M, raw_ostream &OS) const {
if (!Vocab) {
@@ -538,38 +695,67 @@ int main(int argc, char **argv) {
return 1;
}
- // Create MIR2Vec tool and initialize vocabulary
+ // Create MIR2Vec tool
MIR2VecTool Tool(*MMI);
- if (!Tool.initializeVocabulary(*M))
- return 1;
+ // Initialize vocabulary. For triplet/entity generation, only layout is
+ // needed For embedding generation, the full vocabulary is needed.
+ //
+ // Note: Unlike IR2Vec, MIR2Vec vocabulary initialization requires
+ // target-specific information for generating the vocabulary layout. So, we
+ // always initialize the vocabulary in this case.
+ if (TripletsSubCmd || EntitiesSubCmd) {
+ if (!Tool.initializeVocabularyForLayout(*M)) {
+ WithColor::error(errs(), ToolName)
+ << "Failed to initialize MIR2Vec vocabulary for layout.\n";
+ return 1;
+ }
+ } else {
+ if (!Tool.initializeVocabulary(*M)) {
+ WithColor::error(errs(), ToolName)
+ << "Failed to initialize MIR2Vec vocabulary.\n";
+ return 1;
+ }
+ }
+ assert(Tool.getVocabulary() &&
+ "MIR2Vec vocabulary should be initialized at this point");
LLVM_DEBUG(dbgs() << "MIR2Vec vocabulary loaded successfully.\n"
<< "Vocabulary dimension: "
<< Tool.getVocabulary()->getDimension() << "\n"
<< "Vocabulary size: "
<< Tool.getVocabulary()->getCanonicalSize() << "\n");
- // Generate embeddings based on subcommand
- if (!FunctionName.empty()) {
- // Process single function
- Function *F = M->getFunction(FunctionName);
- if (!F) {
- WithColor::error(errs(), ToolName)
- << "Function '" << FunctionName << "' not found\n";
- return 1;
- }
+ // Handle subcommands
+ if (TripletsSubCmd) {
+ Tool.generateTriplets(*M, OS);
+ } else if (EntitiesSubCmd) {
+ Tool.generateEntityMappings(OS);
+ } else if (EmbeddingsSubCmd) {
+ if (!FunctionName.empty()) {
+ // Process single function
+ Function *F = M->getFunction(FunctionName);
+ if (!F) {
+ WithColor::error(errs(), ToolName)
+ << "Function '" << FunctionName << "' not found\n";
+ return 1;
+ }
- MachineFunction *MF = MMI->getMachineFunction(*F);
- if (!MF) {
- WithColor::error(errs(), ToolName)
- << "No MachineFunction for " << FunctionName << "\n";
- return 1;
- }
+ MachineFunction *MF = MMI->getMachineFunction(*F);
+ if (!MF) {
+ WithColor::error(errs(), ToolName)
+ << "No MachineFunction for " << FunctionName << "\n";
+ return 1;
+ }
- Tool.generateEmbeddings(*MF, OS);
+ Tool.generateEmbeddings(*MF, OS);
+ } else {
+ // Process all functions
+ Tool.generateEmbeddings(*M, OS);
+ }
} else {
- // Process all functions
- Tool.generateEmbeddings(*M, OS);
+ WithColor::error(errs(), ToolName)
+ << "Please specify a subcommand: triplets, entities, or embeddings\n";
+ return 1;
}
return 0;
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