[llvm] [DAGCombine] Improve bswap loweing for machines that support bit rotates (PR #164848)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 94eb45e2d..3accdb722 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9901,10 +9901,14 @@ SDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
   case MVT::i32:
     if (isOperationLegal(ISD::ROTR, VT)) {
       // (x & 0x00FF00FF) rotl 8 | (x rotr 8) & 0x00FF00FF
-      SDValue And = DAG.getNode(ISD::AND, dl, VT, Op, DAG.getConstant(0x00FF00FF, dl, VT));
-      SDValue Rotl = DAG.getNode(ISD::ROTL, dl, VT, And, DAG.getConstant(8, dl, SHVT));
-      SDValue Rotr = DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
-      SDValue And2 = DAG.getNode(ISD::AND, dl, VT, Rotr, DAG.getConstant(0x00FF00FF, dl, VT));
+      SDValue And = DAG.getNode(ISD::AND, dl, VT, Op,
+                                DAG.getConstant(0x00FF00FF, dl, VT));
+      SDValue Rotl =
+          DAG.getNode(ISD::ROTL, dl, VT, And, DAG.getConstant(8, dl, SHVT));
+      SDValue Rotr =
+          DAG.getNode(ISD::ROTR, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
+      SDValue And2 = DAG.getNode(ISD::AND, dl, VT, Rotr,
+                                 DAG.getConstant(0x00FF00FF, dl, VT));
       return DAG.getNode(ISD::OR, dl, VT, Rotl, And2);
     }
     Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));

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https://github.com/llvm/llvm-project/pull/164848