[llvm] [PowerPC] Add Implementation and test for new eTCE instructions (PR #164002)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 23 08:14:37 PDT 2025
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/164002
>From 974809175a42d35b0a50284897b7ac10c739e525 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Tue, 7 Oct 2025 20:09:01 +0000
Subject: [PATCH 1/6] Add implementation and encoding tests for tlbsyncio &
ptesyncio
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 13 +++++++++++++
.../Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 6 ++++++
.../PowerPC/ppc64le-encoding-ISAFuture.txt | 6 ++++++
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 8 ++++++++
4 files changed, 33 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 1aefea1a1c498..732e34f63cb9c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -11,6 +11,15 @@
//
//===----------------------------------------------------------------------===//
+class XForm_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern> : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> RS;
+
+ let Pattern = pattern;
+ let Inst{6...10} = RS;
+ let Inst{21...30} = xo;
+}
+
class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
@@ -294,6 +303,10 @@ let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
"$RT, $L, $RA, $RB", []>;
+ def TLBSYNCIO
+ : XForm_RS5<31, 564, (outs), (ins g8rc:$RS), "tlbsyncio $RS", []>;
+ def PTESYNCIO
+ : XForm_RS5<31, 596, (outs), (ins g8rc:$RS), "ptesyncio $RS", []>;
}
let Predicates = [HasVSX, IsISAFuture] in {
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index cdfc8ce9e0ca5..73b8f46267409 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -7,6 +7,12 @@
# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \
# RUN: -mcpu=future | FileCheck %s
+#CHECK: tlbsyncio 15
+0x7d,0xe0,0x04,0x68
+
+#CHECK: ptesyncio 15
+0x7d,0xe0,0x04,0xa8
+
#CHECK: dmxxextfdmr512 2, 34, 1, 0
0xf0 0x82 0x17 0x12
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index f7e314fc819e4..c6425dde4a93e 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -1,6 +1,12 @@
# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown \
# RUN: -mcpu=future | FileCheck %s
+#CHECK: tlbsyncio 15
+0x68,0x04,0xe0,0x7d
+
+#CHECK: ptesyncio 15
+0xa8,0x04,0xe0,0x7d
+
#CHECK: dmxxextfdmr512 2, 34, 1, 0
0x12 0x17 0x82 0xf0
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 29fedd7c20646..c4687f19a339b 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -5,6 +5,14 @@
# RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-BE %s
+# CHECK-BE: tlbsyncio 15 # encoding: [0x7d,0xe0,0x04,0x68]
+# CHECK-LE: tlbsyncio 15 # encoding: [0x68,0x04,0xe0,0x7d]
+ tlbsyncio 15
+
+# CHECK-BE: ptesyncio 15 # encoding: [0x7d,0xe0,0x04,0xa8]
+# CHECK-LE: ptesyncio 15 # encoding: [0xa8,0x04,0xe0,0x7d]
+ ptesyncio 15
+
# CHECK-BE: dmxxextfdmr512 2, 34, 1, 0 # encoding: [0xf0,0x82,0x17,0x12]
# CHECK-LE: dmxxextfdmr512 2, 34, 1, 0 # encoding: [0x12,0x17,0x82,0xf0]
dmxxextfdmr512 2, 34, 1, 0
>From 17be99c099a957bc407d80322c3468d46fed205f Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 9 Oct 2025 20:54:37 +0000
Subject: [PATCH 2/6] add class introduced in update for ISA3.0 tlbie
---
llvm/lib/Target/PowerPC/PPCInstrFormats.td | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index fba1c6609dba0..98c5f09260811 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -850,6 +850,26 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}
+class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+
+ bits<5> RS;
+ bits<5> RB;
+ bits<2> RIC;
+ bits<1> PRS;
+ bits<1> R;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = RS;
+ let Inst{12...13} = RIC;
+ let Inst{14} = PRS;
+ let Inst{15} = R;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
+}
+
class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
dag OOL, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern>
>From bf89a688440b6880560d5d1adc32e7f67a306752 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 9 Oct 2025 21:15:59 +0000
Subject: [PATCH 3/6] add encoding and tests for tlbiep
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 11 +++++++++++
.../Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 3 +++
.../PowerPC/ppc64le-encoding-ISAFuture.txt | 3 +++
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 4 ++++
4 files changed, 21 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 732e34f63cb9c..9cc820447b51d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -307,6 +307,17 @@ let Predicates = [IsISAFuture] in {
: XForm_RS5<31, 564, (outs), (ins g8rc:$RS), "tlbsyncio $RS", []>;
def PTESYNCIO
: XForm_RS5<31, 596, (outs), (ins g8rc:$RS), "ptesyncio $RS", []>;
+ def TLBIEP : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
+ (ins gprc:$RB, gprc:$RS, u2imm:$RIC,
+ u1imm:$PRS, u1imm:$R),
+ "tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
+ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+ def TLBIEP8
+ : XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
+ (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
+ u1imm:$PRS, u1imm:$R),
+ "tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
+ }
}
let Predicates = [HasVSX, IsISAFuture] in {
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 73b8f46267409..c710dda8d4c8a 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -7,6 +7,9 @@
# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \
# RUN: -mcpu=future | FileCheck %s
+#CHECK: tlbiep 8, 10, 2, 1, 0
+0x7d, 0x4a, 0x40, 0x64
+
#CHECK: tlbsyncio 15
0x7d,0xe0,0x04,0x68
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index c6425dde4a93e..cc8780a93d2a5 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -1,6 +1,9 @@
# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown \
# RUN: -mcpu=future | FileCheck %s
+#CHECK: tlbiep 8, 10, 2, 1, 0
+0x64, 0x40, 0x4a, 0x7d
+
#CHECK: tlbsyncio 15
0x68,0x04,0xe0,0x7d
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index c4687f19a339b..27524f93a28fe 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -5,6 +5,10 @@
# RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-BE %s
+#CHECK-BE: tlbiep 8, 10, 2, 1, 0 # encoding: [0x7d,0x4a,0x40,0x64]
+#CHECK-LE: tlbiep 8, 10, 2, 1, 0 # encoding: [0x64,0x40,0x4a,0x7d]
+ tlbiep 8, 10, 2, 1, 0
+
# CHECK-BE: tlbsyncio 15 # encoding: [0x7d,0xe0,0x04,0x68]
# CHECK-LE: tlbsyncio 15 # encoding: [0x68,0x04,0xe0,0x7d]
tlbsyncio 15
>From 401c45007a99f6b8d5ebd652cc49c99d4288ded6 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 17 Oct 2025 19:02:14 +0000
Subject: [PATCH 4/6] update test format
---
.../test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 6 +++---
.../MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index c710dda8d4c8a..5400cf6996c4c 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -8,13 +8,13 @@
# RUN: -mcpu=future | FileCheck %s
#CHECK: tlbiep 8, 10, 2, 1, 0
-0x7d, 0x4a, 0x40, 0x64
+0x7d 0x4a 0x40 0x64
#CHECK: tlbsyncio 15
-0x7d,0xe0,0x04,0x68
+0x7d 0xe0 0x04 0x68
#CHECK: ptesyncio 15
-0x7d,0xe0,0x04,0xa8
+0x7d 0xe0 0x04 0xa8
#CHECK: dmxxextfdmr512 2, 34, 1, 0
0xf0 0x82 0x17 0x12
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index cc8780a93d2a5..5260fd19f940e 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -2,13 +2,13 @@
# RUN: -mcpu=future | FileCheck %s
#CHECK: tlbiep 8, 10, 2, 1, 0
-0x64, 0x40, 0x4a, 0x7d
+0x64 0x40 0x4a 0x7d
#CHECK: tlbsyncio 15
-0x68,0x04,0xe0,0x7d
+0x68 0x04 0xe0 0x7d
#CHECK: ptesyncio 15
-0xa8,0x04,0xe0,0x7d
+0xa8 0x04 0xe0 0x7d
#CHECK: dmxxextfdmr512 2, 34, 1, 0
0x12 0x17 0x82 0xf0
>From 313aecc09c135ad7cb455a7246e58f2bf9925761 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 17 Oct 2025 19:04:47 +0000
Subject: [PATCH 5/6] update class inheritance as intermediate is needed for
next patch
---
llvm/lib/Target/PowerPC/PPCInstrFormats.td | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 98c5f09260811..13e00e67d6be6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -850,26 +850,33 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}
-class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+class XForm_RSB5_UIMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<5> RS;
bits<5> RB;
bits<2> RIC;
- bits<1> PRS;
- bits<1> R;
let Pattern = pattern;
let Inst{6...10} = RS;
let Inst{12...13} = RIC;
- let Inst{14} = PRS;
- let Inst{15} = R;
let Inst{16...20} = RB;
let Inst{21...30} = xo;
}
+class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : XForm_RSB5_UIMM2<opcode, xo, OOL, IOL, asmstr, pattern> {
+
+ bits<1> PRS;
+ bits<1> R;
+
+ let Inst{14} = PRS;
+ let Inst{15} = R;
+}
+
class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
dag OOL, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern>
>From f08d1a66717c2e1e9a295b3e55fc7f32f3bf50ef Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 23 Oct 2025 15:21:11 +0000
Subject: [PATCH 6/6] add def and test for tlbieio
---
llvm/lib/Target/PowerPC/PPCInstrFormats.td | 3 +++
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 6 ++++++
.../test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 3 +++
.../MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt | 3 +++
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 4 ++++
5 files changed, 19 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 13e00e67d6be6..1a77b00588311 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -861,9 +861,12 @@ class XForm_RSB5_UIMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
let Inst{6...10} = RS;
+ let Inst{11} = 0;
let Inst{12...13} = RIC;
+ let Inst{14...15} = 0;
let Inst{16...20} = RB;
let Inst{21...30} = xo;
+ let Inst{31} = 0;
}
class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 9cc820447b51d..b0bed71c6755f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -16,8 +16,11 @@ class XForm_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RS;
let Pattern = pattern;
+
let Inst{6...10} = RS;
+ let Inst{11...20} = 0;
let Inst{21...30} = xo;
+ let Inst{31} = 0;
}
class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
@@ -311,6 +314,9 @@ let Predicates = [IsISAFuture] in {
(ins gprc:$RB, gprc:$RS, u2imm:$RIC,
u1imm:$PRS, u1imm:$R),
"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
+ def TLBIEIO
+ : XForm_RSB5_UIMM2<31, 18, (outs), (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC),
+ "tlbieio $RB, $RS, $RIC", []>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def TLBIEP8
: XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 5400cf6996c4c..054489ce51a60 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -10,6 +10,9 @@
#CHECK: tlbiep 8, 10, 2, 1, 0
0x7d 0x4a 0x40 0x64
+#CHECK: tlbieio 8, 10, 2
+0x7d 0x48 0x40 0x24
+
#CHECK: tlbsyncio 15
0x7d 0xe0 0x04 0x68
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 5260fd19f940e..17d1413bacc3a 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -4,6 +4,9 @@
#CHECK: tlbiep 8, 10, 2, 1, 0
0x64 0x40 0x4a 0x7d
+#CHECK: tlbieio 8, 10, 2
+0x24 0x40 0x48 0x7d
+
#CHECK: tlbsyncio 15
0x68 0x04 0xe0 0x7d
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 27524f93a28fe..e5bc1f47bf666 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -9,6 +9,10 @@
#CHECK-LE: tlbiep 8, 10, 2, 1, 0 # encoding: [0x64,0x40,0x4a,0x7d]
tlbiep 8, 10, 2, 1, 0
+# CHECK-BE: tlbieio 8, 10, 2 # encoding: [0x7d,0x48,0x40,0x24]
+# CHECK-LE: tlbieio 8, 10, 2 # encoding: [0x24,0x40,0x48,0x7d]
+ tlbieio 8, 10, 2
+
# CHECK-BE: tlbsyncio 15 # encoding: [0x7d,0xe0,0x04,0x68]
# CHECK-LE: tlbsyncio 15 # encoding: [0x68,0x04,0xe0,0x7d]
tlbsyncio 15
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