[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 23 02:58:47 PDT 2025
================
@@ -103,18 +115,34 @@ bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
ModifiedRegUnits.init(*TRI);
UsedRegUnits.init(*TRI);
- for (MachineBasicBlock &MBB : Fn) {
- LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+ if (Subtarget.useMIPSLoadStorePairs()) {
+ for (MachineBasicBlock &MBB : Fn) {
+ LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+ for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+ if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+ tryToPairLdStInst(MBBI))
+ MadeChange = true;
+ else
+ ++MBBI;
+ }
+ }
+ }
- for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- MBBI != E;) {
- if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
- tryToPairLdStInst(MBBI))
- MadeChange = true;
- else
- ++MBBI;
+ if (!Subtarget.is64Bit() && Subtarget.hasStdExtZilsd()) {
+ for (auto &MBB : Fn) {
+ for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E;) {
+ if (fixInvalidRegPairOp(MBB, MBBI)) {
+ MadeChange = true;
+ // Iterator was updated by fixInvalidRegPairOp
+ } else {
+ ++MBBI;
+ }
+ }
----------------
4vtomat wrote:
Does it mean both `tryToPairLdStInst` and `fixInvalidRegPairOp` will be run if `cond1 || cond2 == true`?
Do you mean:
```
if (Subtarget.useMIPSLoadStorePairs() ||
(!Subtarget.is64Bit() && Subtarget.hasStdExtZilsd())) {
for (MachineBasicBlock &MBB : Fn) {
LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
MBBI != E;) {
// Both Mips load/store pairing and Zilsd decomposition happen here.
if ((TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
tryToPairLdStInst(MBBI)) ||
fixInvalidRegPairOp(MBB, MBBI))
MadeChange = true;
else
++MBBI;
}
}
}
```
https://github.com/llvm/llvm-project/pull/158640
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