[llvm] [LoongArch][NFC] Pre-commit tests for vector fpext from vxf32 to vxf64 (PR #164740)
Zhaoxin Yang via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 22 18:13:50 PDT 2025
https://github.com/ylzsx updated https://github.com/llvm/llvm-project/pull/164740
>From 1014b2a1018b5ded88f5a23c7a1fddf7725e1a63 Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Mon, 20 Oct 2025 14:21:51 +0800
Subject: [PATCH] [LoongArch][NFC] Pre-commit tests for vector fpext from vxf32
to vxf64
---
.../LoongArch/lasx/ir-instruction/fpext.ll | 64 +++++++++++++++++
.../LoongArch/lsx/ir-instruction/fpext.ll | 71 +++++++++++++++++++
2 files changed, 135 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fpext.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fpext.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fpext.ll
new file mode 100644
index 0000000000000..9c370dd78fad2
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fpext.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK
+
+define void @fpext_v4f32_to_v4f64(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fpext_v4f32_to_v4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vreplvei.w $vr1, $vr0, 3
+; CHECK-NEXT: fcvt.d.s $fa1, $fa1
+; CHECK-NEXT: vreplvei.w $vr2, $vr0, 2
+; CHECK-NEXT: fcvt.d.s $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
+; CHECK-NEXT: fcvt.d.s $fa1, $fa1
+; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0
+; CHECK-NEXT: fcvt.d.s $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr2, 2
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x float>, ptr %a0
+ %ext = fpext <4 x float> %v0 to <4 x double>
+ store <4 x double> %ext, ptr %res
+ ret void
+}
+
+define void @fpext_v8f32_to_v8f64(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fpext_v8f32_to_v8f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
+; CHECK-NEXT: vreplvei.w $vr2, $vr1, 3
+; CHECK-NEXT: fcvt.d.s $fa2, $fa2
+; CHECK-NEXT: vreplvei.w $vr3, $vr1, 2
+; CHECK-NEXT: fcvt.d.s $fa3, $fa3
+; CHECK-NEXT: vextrins.d $vr3, $vr2, 16
+; CHECK-NEXT: vreplvei.w $vr2, $vr1, 1
+; CHECK-NEXT: fcvt.d.s $fa2, $fa2
+; CHECK-NEXT: vreplvei.w $vr1, $vr1, 0
+; CHECK-NEXT: fcvt.d.s $fa1, $fa1
+; CHECK-NEXT: vextrins.d $vr1, $vr2, 16
+; CHECK-NEXT: xvpermi.q $xr1, $xr3, 2
+; CHECK-NEXT: vreplvei.w $vr2, $vr0, 3
+; CHECK-NEXT: fcvt.d.s $fa2, $fa2
+; CHECK-NEXT: vreplvei.w $vr3, $vr0, 2
+; CHECK-NEXT: fcvt.d.s $fa3, $fa3
+; CHECK-NEXT: vextrins.d $vr3, $vr2, 16
+; CHECK-NEXT: vreplvei.w $vr2, $vr0, 1
+; CHECK-NEXT: fcvt.d.s $fa2, $fa2
+; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0
+; CHECK-NEXT: fcvt.d.s $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr2, 16
+; CHECK-NEXT: xvpermi.q $xr0, $xr3, 2
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: xvst $xr1, $a0, 32
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <8 x float>, ptr %a0
+ %ext = fpext <8 x float> %v0 to <8 x double>
+ store <8 x double> %ext, ptr %res
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll
new file mode 100644
index 0000000000000..e2bf8ab71d8ea
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+
+;; fpext
+define void @fpext_v1f32_to_v1f64(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fpext_v1f32_to_v1f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fld.s $fa0, $a1, 0
+; CHECK-NEXT: fcvt.d.s $fa0, $fa0
+; CHECK-NEXT: fst.d $fa0, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <1 x float>, ptr %a0
+ %ext = fpext <1 x float> %v0 to <1 x double>
+ store <1 x double> %ext, ptr %res
+ ret void
+}
+
+define void @fpext_v2f32_to_v2f64(ptr %res, ptr %a0) nounwind {
+; LA32-LABEL: fpext_v2f32_to_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: fld.s $fa0, $a1, 4
+; LA32-NEXT: fld.s $fa1, $a1, 0
+; LA32-NEXT: fcvt.d.s $fa0, $fa0
+; LA32-NEXT: fcvt.d.s $fa1, $fa1
+; LA32-NEXT: vextrins.d $vr1, $vr0, 16
+; LA32-NEXT: vst $vr1, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: fpext_v2f32_to_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a1, $a1, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
+; LA64-NEXT: vreplvei.w $vr1, $vr0, 1
+; LA64-NEXT: fcvt.d.s $fa1, $fa1
+; LA64-NEXT: vreplvei.w $vr0, $vr0, 0
+; LA64-NEXT: fcvt.d.s $fa0, $fa0
+; LA64-NEXT: vextrins.d $vr0, $vr1, 16
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
+entry:
+ %v0 = load <2 x float>, ptr %a0
+ %ext = fpext <2 x float> %v0 to <2 x double>
+ store <2 x double> %ext, ptr %res
+ ret void
+}
+
+define void @fpext_v4f32_to_v4f64(ptr %res, ptr %a0) nounwind {
+; CHECK-LABEL: fpext_v4f32_to_v4f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
+; CHECK-NEXT: fcvt.d.s $fa1, $fa1
+; CHECK-NEXT: vreplvei.w $vr2, $vr0, 0
+; CHECK-NEXT: fcvt.d.s $fa2, $fa2
+; CHECK-NEXT: vextrins.d $vr2, $vr1, 16
+; CHECK-NEXT: vreplvei.w $vr1, $vr0, 3
+; CHECK-NEXT: fcvt.d.s $fa1, $fa1
+; CHECK-NEXT: vreplvei.w $vr0, $vr0, 2
+; CHECK-NEXT: fcvt.d.s $fa0, $fa0
+; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
+; CHECK-NEXT: vst $vr0, $a0, 16
+; CHECK-NEXT: vst $vr2, $a0, 0
+; CHECK-NEXT: ret
+entry:
+ %v0 = load <4 x float>, ptr %a0
+ %ext = fpext <4 x float> %v0 to <4 x double>
+ store <4 x double> %ext, ptr %res
+ ret void
+}
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