[llvm] [RISCV] Add short forward branch support for `min`, `max`, `maxu` and `minu` (PR #164394)

[Craig Topper via llvm-commits]

topperc wrote:

> > SiFive cores do not support short forward branch for MIN/MAX.
> 
> We did it this way to avoid introducing tune features that depend on other tune features, but I see there are more instruction differences than I expected. I hoped that SiFive cores might not have Zbb when they don't do this fusion, but I should have checked closer.
> 
> Our plan is to add another feature to enable these SFB cases, which would be required. I was originally thinking of naming it `TuneShortForwardBranchOptZbb`, but I see there are already Zbb instructions supported by SFB that you presumably don't want disabled if you don't support SFB for min/max (SFB for ANDN, ORN, XNOR).
> 
> The hypothetical `TuneShortForwardBranchOptZbb` would require/imply `TuneShortForwardBranchOpt`, and the former would be required to SFB min/max.
> 
> The idea behind this naming scheme is it should be obvious for extending to other extensions, as I think we will also want it for a `TuneShortForwardBranchOptZmmul` (or similar), as you've said you don't fuse branches with MUL.
> 
> What are your thoughts?
> 
> I've asked Harsh to prepare this patch update (as well as other updates), but it would be good to hear you like this direction before we upload the next version.

I'm not sure what a good name is. The instructions that aren't supported are the ones that are only available on PipeB in RISCVSchedSiFive7.td. That includes div/rem, mul, ctz, ctz, ctpop, rotate, shXadd, orc.b, bset(i), bclr(i), binv(i).

Maybe we should rename the existing flag to TuneShortForwardBranchOptIALU? IALU being the scheduler class that covers the supported instructions?

https://github.com/llvm/llvm-project/pull/164394