[llvm] [AArch64] Initial sched model for Neoverse V3, V3AE (PR #163932)

[Simon Wallis via llvm-commits]

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@@ -2532,18 +2532,18 @@ drps
 # CHECK-NEXT:  1      1     0.13                        orn	w2, w5, w29
 # CHECK-NEXT:  1      2     0.50                        ands	w7, wzr, w9, lsl #1
 # CHECK-NEXT:  1      2     0.50                        ands	x3, x5, x20, ror #63
-# CHECK-NEXT:  1      1     0.13                        bics	w3, w5, w7
+# CHECK-NEXT:  1      1     0.25                        bics	w3, w5, w7
 # CHECK-NEXT:  1      2     0.50                        bics	x3, xzr, x3, lsl #1
 # CHECK-NEXT:  1      2     0.50                        tst	w3, w7, lsl #31
 # CHECK-NEXT:  1      2     0.50                        tst	x2, x20, asr #2
-# CHECK-NEXT:  1      0     0.13                        mov	x3, x6
-# CHECK-NEXT:  1      0     0.13                        mov	x3, xzr
-# CHECK-NEXT:  1      0     0.13                        mov	wzr, w2
-# CHECK-NEXT:  1      0     0.13                        mov	w3, w5
+# CHECK-NEXT:  1      0     0.10                        mov	x3, x6
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simonwallis2 wrote:

I think it's OK.
4.11 Zero Latency MOVs A subset of register-to-register move operations and move immediate operations are executed with zero latency. These instructions do not utilize the scheduling and execution resources of the machine. 
So in the V3 model, mov x3,x6 is constrained only by the IssueWidth, currently 10.

https://github.com/llvm/llvm-project/pull/163932