[llvm] [FastIsel] Get the right register type for call instruction (PR #164565)

[Luo Yuanke via llvm-commits]

https://github.com/LuoYuanke created https://github.com/llvm/llvm-project/pull/164565

When switch from fast isel to dag isel the input value is from llvm IR instruction.
If the instruction is call we should get the calling convention of the callee and
pass it to RegsForValue::getCopyFromRegs, so that it can deduce the right RegisterVT
of the returned value of the callee.


>From 6865dee726d0eeaf63094f27ad9c21e8c25da6c4 Mon Sep 17 00:00:00 2001
From: Yuanke Luo <ykluo at birentech.com>
Date: Wed, 22 Oct 2025 11:49:42 +0800
Subject: [PATCH] [FastIsel] Get the right register type for call instruction

When switch from fast isel to dag isel the input value is from llvm IR instruction.
If the instruction is call we should get the calling convention of the callee and
pass it to RegsForValue::getCopyFromRegs, so that it can deduce the right RegisterVT
of the returned value of the callee.
---
 .../SelectionDAG/SelectionDAGBuilder.cpp      |  7 ++++++-
 llvm/test/CodeGen/X86/bf16-fast-isel.ll       | 19 +++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/X86/bf16-fast-isel.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 20a0efd3afa1c..14f9fdfddf658 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1977,8 +1977,13 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
   if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
     Register InReg = FuncInfo.InitializeRegForValue(Inst);
 
+    std::optional<CallingConv::ID> CallConv = std::nullopt;
+    auto *Callee = dyn_cast<CallInst>(Inst);
+    if (Callee && !Callee->isInlineAsm())
+      CallConv = Callee->getCallingConv();
+
     RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
-                     Inst->getType(), std::nullopt);
+                     Inst->getType(), CallConv);
     SDValue Chain = DAG.getEntryNode();
     return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
   }
diff --git a/llvm/test/CodeGen/X86/bf16-fast-isel.ll b/llvm/test/CodeGen/X86/bf16-fast-isel.ll
new file mode 100644
index 0000000000000..43622566d2974
--- /dev/null
+++ b/llvm/test/CodeGen/X86/bf16-fast-isel.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @test(ptr %f) nounwind {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    callq foo at PLT
+; CHECK-NEXT:    callq bar at PLT
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+entry:
+  %call = call bfloat @foo(ptr %f)
+  %call2 = call noundef zeroext i8 @bar(bfloat %call)
+  ret i8 %call2
+}
+
+declare bfloat @foo(ptr %f)
+declare zeroext i8 @bar(bfloat)