[llvm] [NVPTX] Lower LLVM masked vector loads and stores to PTX (PR #159387)

[Princeton Ferro via llvm-commits]

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@@ -2918,10 +2918,9 @@ static SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) {
   assert(Mask.getValueType().getVectorNumElements() ==
              ValVT.getVectorNumElements() &&
          "Mask size must be the same as the vector size");
-  for (unsigned I : llvm::seq(ValVT.getVectorNumElements())) {
-    assert(isa<ConstantSDNode>(Mask.getOperand(I)) &&
-           "Mask elements must be constants");
-    if (Mask->getConstantOperandVal(I) == 0) {
+  for (auto [I, Op] : enumerate(Mask->ops())) {
+    // Mask elements must be constants.
+    if (Op.getNode()->getAsZExtVal() == 0) {
----------------
Prince781 wrote:

```suggestion
    if (Op->getAsZExtVal() == 0) {
```

https://github.com/llvm/llvm-project/pull/159387