[llvm] [WebAssembly] [Codegen] Add pattern for relaxed min max from fminimum/fmaximum over v4f32 and v2f64 (PR #162948)
Jasmine Tang via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 21 09:26:52 PDT 2025
https://github.com/badumbatish updated https://github.com/llvm/llvm-project/pull/162948
>From 33e285cac2b051b0a042b4f874a1702ca85c3e1f Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Fri, 10 Oct 2025 16:57:54 -0700
Subject: [PATCH 1/4] Precommit test for relaxed min max
---
.../CodeGen/WebAssembly/simd-relaxed-fmax.ll | 35 +++++++++++++++++++
.../CodeGen/WebAssembly/simd-relaxed-fmin.ll | 34 ++++++++++++++++++
2 files changed, 69 insertions(+)
create mode 100644 llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
new file mode 100644
index 0000000000000..d54ad2a084e5c
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+
+; RUN: llc < %s -mtriple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd | FileCheck %s
+
+; Test that fminimum and fmaximum get transformed to relaxed_min and relaxed_max
+
+target triple = "wasm32"
+
+define <4 x float> @test_max_f32x4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_max_f32x4:
+; CHECK: .functype test_max_f32x4 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f32x4.max
+; CHECK-NEXT: # fallthrough-return
+ %result = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b)
+ ret <4 x float> %result
+}
+
+
+define <2 x double> @test_max_f64x2(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_max_f64x2:
+; CHECK: .functype test_max_f64x2 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f64x2.max
+; CHECK-NEXT: # fallthrough-return
+ %result = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
+ ret <2 x double> %result
+}
+
+declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
new file mode 100644
index 0000000000000..11f96181914d7
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd | FileCheck %s
+
+; Test that fminimum and fmaximum get transformed to relaxed_min and relaxed_max
+
+target triple = "wasm32"
+
+define <4 x float> @test_min_f32x4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_min_f32x4:
+; CHECK: .functype test_min_f32x4 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f32x4.min
+; CHECK-NEXT: # fallthrough-return
+ %result = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
+ ret <4 x float> %result
+}
+
+
+define <2 x double> @test_min_f64x2(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_min_f64x2:
+; CHECK: .functype test_min_f64x2 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f64x2.min
+; CHECK-NEXT: # fallthrough-return
+ %result = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
+ ret <2 x double> %result
+}
+
+declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)
>From 944fdbeb134006a8b480c75cf9514d838e9f70d2 Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Fri, 10 Oct 2025 16:58:07 -0700
Subject: [PATCH 2/4] Add implementation
---
.../WebAssembly/WebAssemblyInstrSIMD.td | 20 +++++++++++++++++++
.../CodeGen/WebAssembly/simd-relaxed-fmax.ll | 4 ++--
.../CodeGen/WebAssembly/simd-relaxed-fmin.ll | 4 ++--
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 49af78bce68c3..0dd5e30ed9c86 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1692,6 +1692,26 @@ defm SIMD_RELAXED_FMIN :
defm SIMD_RELAXED_FMAX :
RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>;
+// Transform standard fminimum/fmaximum to relaxed versions
+// AddedComplexity ensures these patterns match before the standard MIN/MAX
+let AddedComplexity = 1 in {
+def : Pat<(v4f32 (fminimum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+def : Pat<(v4f32 (fmaximum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+def : Pat<(v2f64 (fminimum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+def : Pat<(v2f64 (fmaximum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+}
+
//===----------------------------------------------------------------------===//
// Relaxed rounding q15 multiplication
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
index d54ad2a084e5c..1339f3a730150 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
@@ -12,7 +12,7 @@ define <4 x float> @test_max_f32x4(<4 x float> %a, <4 x float> %b) {
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
-; CHECK-NEXT: f32x4.max
+; CHECK-NEXT: f32x4.relaxed_max
; CHECK-NEXT: # fallthrough-return
%result = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %result
@@ -25,7 +25,7 @@ define <2 x double> @test_max_f64x2(<2 x double> %a, <2 x double> %b) {
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
-; CHECK-NEXT: f64x2.max
+; CHECK-NEXT: f64x2.relaxed_max
; CHECK-NEXT: # fallthrough-return
%result = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
ret <2 x double> %result
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
index 11f96181914d7..799cc4a45144c 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
@@ -11,7 +11,7 @@ define <4 x float> @test_min_f32x4(<4 x float> %a, <4 x float> %b) {
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
-; CHECK-NEXT: f32x4.min
+; CHECK-NEXT: f32x4.relaxed_min
; CHECK-NEXT: # fallthrough-return
%result = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %result
@@ -24,7 +24,7 @@ define <2 x double> @test_min_f64x2(<2 x double> %a, <2 x double> %b) {
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
-; CHECK-NEXT: f64x2.min
+; CHECK-NEXT: f64x2.relaxed_min
; CHECK-NEXT: # fallthrough-return
%result = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
ret <2 x double> %result
>From 653c167ae3d773a99058ef2ff2e424403d907a4b Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Mon, 20 Oct 2025 12:41:31 -0700
Subject: [PATCH 3/4] Replace min/max with fminnum fminimumnum fmaxnum
fmaximumnum
---
.../WebAssembly/WebAssemblyISelLowering.cpp | 5 ++
.../WebAssembly/WebAssemblyInstrSIMD.td | 40 +++++++++++-----
.../CodeGen/WebAssembly/simd-relaxed-fmax.ll | 47 ++++++++++++++-----
.../CodeGen/WebAssembly/simd-relaxed-fmin.ll | 47 ++++++++++++++-----
4 files changed, 105 insertions(+), 34 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 64723340051b8..70c9e499945fe 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -183,6 +183,11 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
for (auto T : {MVT::i32, MVT::i64})
setOperationAction(Op, T, Custom);
+ if (Subtarget->hasRelaxedSIMD()) {
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM},
+ {MVT::v4f32, MVT::v2f64}, Legal);
+ }
// SIMD-specific configuration
if (Subtarget->hasSIMD128()) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 0dd5e30ed9c86..c165de5f18678 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1695,21 +1695,37 @@ defm SIMD_RELAXED_FMAX :
// Transform standard fminimum/fmaximum to relaxed versions
// AddedComplexity ensures these patterns match before the standard MIN/MAX
let AddedComplexity = 1 in {
-def : Pat<(v4f32 (fminimum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+ def : Pat<(v4f32 (fminnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
-def : Pat<(v4f32 (fmaximum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+ def : Pat<(v4f32 (fminimumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
-def : Pat<(v2f64 (fminimum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+ def : Pat<(v4f32 (fmaxnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
-def : Pat<(v2f64 (fmaximum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+ def : Pat<(v4f32 (fmaximumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+ def : Pat<(v2f64 (fminnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+ def : Pat<(v2f64 (fminimumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+ def : Pat<(v2f64 (fmaxnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
+
+ def : Pat<(v2f64 (fmaximumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
index 1339f3a730150..45f4ddd783a55 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmax.ll
@@ -2,34 +2,59 @@
; RUN: llc < %s -mtriple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd | FileCheck %s
-; Test that fminimum and fmaximum get transformed to relaxed_min and relaxed_max
+; Test that fmaxnum and fmaximumnum get transformed to relaxed_max
target triple = "wasm32"
-define <4 x float> @test_max_f32x4(<4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: test_max_f32x4:
-; CHECK: .functype test_max_f32x4 (v128, v128) -> (v128)
+define <4 x float> @test_maxnum_f32x4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_maxnum_f32x4:
+; CHECK: .functype test_maxnum_f32x4 (v128, v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: f32x4.relaxed_max
; CHECK-NEXT: # fallthrough-return
- %result = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b)
+ %result = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %result
}
+define <4 x float> @test_maximumnum_f32x4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_maximumnum_f32x4:
+; CHECK: .functype test_maximumnum_f32x4 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f32x4.relaxed_max
+; CHECK-NEXT: # fallthrough-return
+ %result = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %a, <4 x float> %b)
+ ret <4 x float> %result
+}
+
+define <2 x double> @test_maxnum_f64x2(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_maxnum_f64x2:
+; CHECK: .functype test_maxnum_f64x2 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f64x2.relaxed_max
+; CHECK-NEXT: # fallthrough-return
+ %result = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b)
+ ret <2 x double> %result
+}
-define <2 x double> @test_max_f64x2(<2 x double> %a, <2 x double> %b) {
-; CHECK-LABEL: test_max_f64x2:
-; CHECK: .functype test_max_f64x2 (v128, v128) -> (v128)
+define <2 x double> @test_minimumnum_f64x2(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_minimumnum_f64x2:
+; CHECK: .functype test_minimumnum_f64x2 (v128, v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: f64x2.relaxed_max
; CHECK-NEXT: # fallthrough-return
- %result = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b)
+ %result = call <2 x double> @llvm.maximumnum.v2f64(<2 x double> %a, <2 x double> %b)
ret <2 x double> %result
}
-declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
-declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)
+declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.maximumnum.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.maximumnum.v2f64(<2 x double>, <2 x double>)
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
index 799cc4a45144c..f3eec023663a7 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-fmin.ll
@@ -1,34 +1,59 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd | FileCheck %s
-; Test that fminimum and fmaximum get transformed to relaxed_min and relaxed_max
+; Test that fminnum and fminimumnum get transformed to relaxed_min
target triple = "wasm32"
-define <4 x float> @test_min_f32x4(<4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: test_min_f32x4:
-; CHECK: .functype test_min_f32x4 (v128, v128) -> (v128)
+define <4 x float> @test_minnum_f32x4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_minnum_f32x4:
+; CHECK: .functype test_minnum_f32x4 (v128, v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: f32x4.relaxed_min
; CHECK-NEXT: # fallthrough-return
- %result = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b)
+ %result = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %result
}
+define <4 x float> @test_minimumnum_f32x4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: test_minimumnum_f32x4:
+; CHECK: .functype test_minimumnum_f32x4 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f32x4.relaxed_min
+; CHECK-NEXT: # fallthrough-return
+ %result = call <4 x float> @llvm.minimumnum.v4f32(<4 x float> %a, <4 x float> %b)
+ ret <4 x float> %result
+}
+
+define <2 x double> @test_minnum_f64x2(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_minnum_f64x2:
+; CHECK: .functype test_minnum_f64x2 (v128, v128) -> (v128)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get 0
+; CHECK-NEXT: local.get 1
+; CHECK-NEXT: f64x2.relaxed_min
+; CHECK-NEXT: # fallthrough-return
+ %result = call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b)
+ ret <2 x double> %result
+}
-define <2 x double> @test_min_f64x2(<2 x double> %a, <2 x double> %b) {
-; CHECK-LABEL: test_min_f64x2:
-; CHECK: .functype test_min_f64x2 (v128, v128) -> (v128)
+define <2 x double> @test_minimumnum_f64x2(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: test_minimumnum_f64x2:
+; CHECK: .functype test_minimumnum_f64x2 (v128, v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: local.get 0
; CHECK-NEXT: local.get 1
; CHECK-NEXT: f64x2.relaxed_min
; CHECK-NEXT: # fallthrough-return
- %result = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b)
+ %result = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %a, <2 x double> %b)
ret <2 x double> %result
}
-declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
-declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)
+declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.fminimumnum.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.fminimumnum.v2f64(<2 x double>, <2 x double>)
>From 657d189e413758501ccb7061cb626551569fc664 Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Tue, 21 Oct 2025 09:21:28 -0700
Subject: [PATCH 4/4] Remove AddedComplexity
---
.../WebAssembly/WebAssemblyInstrSIMD.td | 51 +++++++++----------
1 file changed, 24 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index c165de5f18678..4d87157aa92c9 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1693,40 +1693,37 @@ defm SIMD_RELAXED_FMAX :
RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>;
// Transform standard fminimum/fmaximum to relaxed versions
-// AddedComplexity ensures these patterns match before the standard MIN/MAX
-let AddedComplexity = 1 in {
- def : Pat<(v4f32 (fminnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v4f32 (fminnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v4f32 (fminimumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v4f32 (fminimumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v4f32 (fmaxnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v4f32 (fmaxnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v4f32 (fmaximumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
- (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v4f32 (fmaximumnum (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F32x4 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v2f64 (fminnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v2f64 (fminnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v2f64 (fminimumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v2f64 (fminimumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMIN_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v2f64 (fmaxnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
+def : Pat<(v2f64 (fmaxnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
- def : Pat<(v2f64 (fmaximumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
- (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
- Requires<[HasRelaxedSIMD]>;
-}
+def : Pat<(v2f64 (fmaximumnum (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
+ (SIMD_RELAXED_FMAX_F64x2 V128:$lhs, V128:$rhs)>,
+ Requires<[HasRelaxedSIMD]>;
//===----------------------------------------------------------------------===//
// Relaxed rounding q15 multiplication
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