[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Petar Avramovic via llvm-commits]

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@@ -500,6 +500,27 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
   MI.eraseFromParent();
 }
 
+void RegBankLegalizeHelper::lowerScalarizeV2S16(MachineInstr &MI) {
+  auto Op1 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(1).getReg());
+  auto Hi1 = Op1.getReg(0);
+  auto Lo1 = Op1.getReg(1);
+  auto Op2 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(2).getReg());
+  auto Hi2 = Op2.getReg(0);
+  auto Lo2 = Op2.getReg(1);
+
+  auto CastHi1 = B.buildZExt(SgprRB_S32, Hi1);
+  auto CastLo1 = B.buildZExt(SgprRB_S32, Lo1);
+  auto CastHi2 = B.buildZExt(SgprRB_S32, Hi2);
+  auto CastLo2 = B.buildZExt(SgprRB_S32, Lo2);
+
+  auto ResHi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {CastHi1, CastHi2});
+  auto ResLo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {CastLo1, CastLo2});
+
+  B.buildBuildVectorTrunc(MI.getOperand(0).getReg(),
+                          {ResHi.getReg(0), ResLo.getReg(0)});
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petar-avramovic wrote:

build vector and similar pack in "little endian way" index 0 are low bits

https://github.com/llvm/llvm-project/pull/159860