[llvm] [RISCV] Support codegen form some scalar P extension instructions. (PR #164359)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 20 22:49:14 PDT 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/164359
This includes sext.b, sext.h, min/max, rev8, clz(w), and abs(w).
Test cases copied from rv32zbb.ll and rv64zbb.ll and pruned to what was needed for P. Eventually we should merge these back into a single test file, but I wanted to keep P separated while it is experimental.
>From e36aa27b22f56161413771a2793541263fe32c64 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 20 Oct 2025 21:52:26 -0700
Subject: [PATCH] [RISCV] Support codegen form some scalar P extension
instructions.
This includes sext.b, sext.h, min/max, rev8, clz(w), and abs(w).
Test cases copied from rv32zbb.ll and rv64zbb.ll and pruned to what
was needed for P. Eventually we should merge these back into a
single test file, but I wanted to keep P separated while it is
experimental.
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 23 +-
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 14 +
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 18 +-
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 +-
llvm/test/CodeGen/RISCV/rv32p.ll | 709 ++++++++++++++
llvm/test/CodeGen/RISCV/rv64p.ll | 963 ++++++++++++++++++++
7 files changed, 1720 insertions(+), 14 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/rv32p.ll
create mode 100644 llvm/test/CodeGen/RISCV/rv64p.ll
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 19992e667d192..e2bfbeb41db9c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1123,7 +1123,8 @@ def HasStdExtZbkbOrP
"'Base P' (Packed-SIMD)">;
def HasStdExtZbbOrZbkbOrP
- : Predicate<"Subtarget->HasStdExtZbbOrZbkb()|| Subtarget->hasStdExtP()">,
+ : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb() || "
+ "Subtarget->hasStdExtP()">,
AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP),
"'Zbb' (Basic Bit-Manipulation) or "
"'Zbkb' (Bitmanip instructions for Cryptography) or "
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0a53ba935b1a7..877695f2ad8de 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -318,8 +318,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
- if (!Subtarget.hasStdExtZbb() && !Subtarget.hasVendorXTHeadBb() &&
- !Subtarget.hasVendorXqcibm() && !Subtarget.hasVendorXAndesPerf() &&
+ if (!Subtarget.hasStdExtZbb() && !Subtarget.hasStdExtP() &&
+ !Subtarget.hasVendorXTHeadBb() && !Subtarget.hasVendorXqcibm() &&
+ !Subtarget.hasVendorXAndesPerf() &&
!(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()))
setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, Expand);
@@ -392,7 +393,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
}
- if (Subtarget.hasStdExtZbb() ||
+ if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtP() ||
(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) {
setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT,
Legal);
@@ -419,14 +420,18 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// We need the custom lowering to make sure that the resulting sequence
// for the 32bit case is efficient on 64bit targets.
// Use default promotion for i32 without Zbb.
- if (Subtarget.is64Bit() && Subtarget.hasStdExtZbb())
+ if (Subtarget.is64Bit() &&
+ (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtP()))
setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTLZ, XLenVT, Expand);
}
- if (Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()) {
+ if (Subtarget.hasStdExtP() ||
+ (Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) {
setOperationAction(ISD::ABS, XLenVT, Legal);
+ if (Subtarget.is64Bit())
+ setOperationAction(ISD::ABS, MVT::i32, Custom);
} else if (Subtarget.hasShortForwardBranchOpt()) {
// We can use PseudoCCSUB to implement ABS.
setOperationAction(ISD::ABS, XLenVT, Legal);
@@ -14791,6 +14796,14 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
+ if (Subtarget.hasStdExtP()) {
+ SDValue Src =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
+ SDValue Abs = DAG.getNode(RISCVISD::ABSW_P, DL, MVT::i64, Src);
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Abs));
+ return;
+ }
+
if (Subtarget.hasStdExtZbb()) {
// Emit a special ABSW node that will be expanded to NEGW+MAX at isel.
// This allows us to remember that the result is sign extended. Expanding
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 7d8a9192d9847..56044d2be4f27 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1455,3 +1455,17 @@ let Predicates = [HasStdExtP, IsRV32] in {
def PMAXU_DW : RVPPairBinaryExchanged_rr<0b1111, 0b01, "pmaxu.dw">;
def PMAXU_DB : RVPPairBinaryExchanged_rr<0b1111, 0b10, "pmaxu.db">;
} // Predicates = [HasStdExtP, IsRV32]
+
+//===----------------------------------------------------------------------===//
+// Codegen patterns
+//===----------------------------------------------------------------------===//
+
+// TODO: Rename RISCVISD::ABSW to RISCVISD::NEGW_MAX or something so this can
+// be RISCVISD::ABSW.
+def riscv_absw_p : RVSDNode<"ABSW_P", SDTIntUnaryOp>;
+
+let Predicates = [HasStdExtP] in
+def : PatGpr<abs, ABS>;
+
+let Predicates = [HasStdExtP, IsRV64] in
+def : PatGpr<riscv_absw_p, ABSW>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 62b7bcd67283a..b895857529208 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -599,14 +599,20 @@ def : PatGpr<riscv_zip, ZIP_RV32, i32>;
def : PatGpr<riscv_unzip, UNZIP_RV32, i32>;
} // Predicates = [HasStdExtZbkb, IsRV32]
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbbOrP] in {
def : PatGpr<ctlz, CLZ>;
+}
+
+let Predicates = [HasStdExtZbb] in {
def : PatGpr<cttz, CTZ>;
def : PatGpr<ctpop, CPOP>;
} // Predicates = [HasStdExtZbb]
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZbbOrP, IsRV64] in {
def : PatGpr<riscv_clzw, CLZW>;
+}
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
def : PatGpr<riscv_ctzw, CTZW>;
def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
@@ -614,22 +620,22 @@ def : Pat<(i64 (riscv_absw GPR:$rs1)),
(MAX GPR:$rs1, (XLenVT (SUBW (XLenVT X0), GPR:$rs1)))>;
} // Predicates = [HasStdExtZbb, IsRV64]
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbbOrP] in {
def : Pat<(XLenVT (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>;
def : Pat<(XLenVT (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
} // Predicates = [HasStdExtZbb]
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbbOrP] in {
def : PatGprGpr<smin, MIN>;
def : PatGprGpr<smax, MAX>;
def : PatGprGpr<umin, MINU>;
def : PatGprGpr<umax, MAXU>;
} // Predicates = [HasStdExtZbb]
-let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in
+let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] in
def : PatGpr<bswap, REV8_RV32, i32>;
-let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in
+let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64] in
def : PatGpr<bswap, REV8_RV64, i64>;
let Predicates = [HasStdExtZbkb] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 334db4bfb75d9..4b4fc8f0d8e76 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -187,7 +187,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
bool hasCLZLike() const {
- return HasStdExtZbb || HasVendorXTHeadBb ||
+ return HasStdExtZbb || HasStdExtP || HasVendorXTHeadBb ||
(HasVendorXCVbitmanip && !IsRV64);
}
bool hasCTZLike() const {
@@ -197,7 +197,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);
}
bool hasREV8Like() const {
- return HasStdExtZbb || HasStdExtZbkb || HasVendorXTHeadBb;
+ return HasStdExtZbb || HasStdExtZbkb || HasStdExtP || HasVendorXTHeadBb;
}
bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; }
diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll
new file mode 100644
index 0000000000000..4eee880a398a9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32p.ll
@@ -0,0 +1,709 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define i32 @ctlz_i32(i32 %a) nounwind {
+; CHECK-LABEL: ctlz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+
+define i64 @ctlz_i64(i64 %a) nounwind {
+; CHECK-LABEL: ctlz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bnez a1, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: addi a0, a0, 32
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: clz a0, a1
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define i32 @cttz_i32(i32 %a) nounwind {
+; CHECK-LABEL: cttz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i64 @cttz_i64(i64 %a) nounwind {
+; CHECK-LABEL: cttz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: or a2, a0, a1
+; CHECK-NEXT: beqz a2, .LBB3_3
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: bnez a0, .LBB3_4
+; CHECK-NEXT: # %bb.2: # %cond.false
+; CHECK-NEXT: addi a0, a1, -1
+; CHECK-NEXT: not a1, a1
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: j .LBB3_5
+; CHECK-NEXT: .LBB3_3:
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_4:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: .LBB3_5: # %cond.false
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+define i32 @sextb_i32(i32 %a) nounwind {
+; CHECK-LABEL: sextb_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 24
+ %shr = ashr exact i32 %shl, 24
+ ret i32 %shr
+}
+
+define i64 @sextb_i64(i64 %a) nounwind {
+; CHECK-LABEL: sextb_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: srai a1, a0, 31
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 56
+ %shr = ashr exact i64 %shl, 56
+ ret i64 %shr
+}
+
+define i32 @sexth_i32(i32 %a) nounwind {
+; CHECK-LABEL: sexth_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 16
+ %shr = ashr exact i32 %shl, 16
+ ret i32 %shr
+}
+
+define i64 @sexth_i64(i64 %a) nounwind {
+; CHECK-LABEL: sexth_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: srai a1, a0, 31
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 48
+ %shr = ashr exact i64 %shl, 48
+ ret i64 %shr
+}
+
+define i32 @min_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: min_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: min a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp slt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @min_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: min_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: slt a4, a1, a3
+; CHECK-NEXT: beqz a4, .LBB9_3
+; CHECK-NEXT: j .LBB9_4
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: bnez a4, .LBB9_4
+; CHECK-NEXT: .LBB9_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB9_4:
+; CHECK-NEXT: ret
+ %cmp = icmp slt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define i32 @max_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: max_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: max a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @max_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: max_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB11_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: slt a4, a3, a1
+; CHECK-NEXT: beqz a4, .LBB11_3
+; CHECK-NEXT: j .LBB11_4
+; CHECK-NEXT: .LBB11_2:
+; CHECK-NEXT: sltu a4, a2, a0
+; CHECK-NEXT: bnez a4, .LBB11_4
+; CHECK-NEXT: .LBB11_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB11_4:
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define i32 @minu_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: minu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @minu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: minu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB13_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: beqz a4, .LBB13_3
+; CHECK-NEXT: j .LBB13_4
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: bnez a4, .LBB13_4
+; CHECK-NEXT: .LBB13_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB13_4:
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define i32 @maxu_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: maxu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: maxu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+; As we are not matching directly i64 code patterns on RV32 some i64 patterns
+; don't have yet any matching bit manipulation instructions on RV32.
+; This test is presented here in case future expansions of the Bitmanip
+; extensions introduce instructions suitable for this pattern.
+
+define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: maxu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB15_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a3, a1
+; CHECK-NEXT: beqz a4, .LBB15_3
+; CHECK-NEXT: j .LBB15_4
+; CHECK-NEXT: .LBB15_2:
+; CHECK-NEXT: sltu a4, a2, a0
+; CHECK-NEXT: bnez a4, .LBB15_4
+; CHECK-NEXT: .LBB15_3:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: .LBB15_4:
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+declare i32 @llvm.abs.i32(i32, i1 immarg)
+
+define i32 @abs_i32(i32 %x) {
+; CHECK-LABEL: abs_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: abs a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 @abs_i64(i64 %x) {
+; CHECK-LABEL: abs_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bgez a1, .LBB17_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: snez a2, a0
+; CHECK-NEXT: neg a0, a0
+; CHECK-NEXT: neg a1, a1
+; CHECK-NEXT: sub a1, a1, a2
+; CHECK-NEXT: .LBB17_2:
+; CHECK-NEXT: ret
+ %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+ ret i64 %abs
+}
+
+define i32 @zexth_i32(i32 %a) nounwind {
+; CHECK-LABEL: zexth_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 16
+; CHECK-NEXT: srli a0, a0, 16
+; CHECK-NEXT: ret
+ %and = and i32 %a, 65535
+ ret i32 %and
+}
+
+define i64 @zexth_i64(i64 %a) nounwind {
+; CHECK-LABEL: zexth_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 16
+; CHECK-NEXT: srli a0, a0, 16
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: ret
+ %and = and i64 %a, 65535
+ ret i64 %and
+}
+
+declare i32 @llvm.bswap.i32(i32)
+
+define i32 @bswap_i32(i32 %a) nounwind {
+; CHECK-LABEL: bswap_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: ret
+ %1 = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %1
+}
+
+declare i64 @llvm.bswap.i64(i64)
+
+define i64 @bswap_i64(i64 %a) {
+; CHECK-LABEL: bswap_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a2, a1
+; CHECK-NEXT: rev8 a1, a0
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.bswap.i64(i64 %a)
+ ret i64 %1
+}
+
+define i32 @srai_slli(i16 signext %0) {
+; CHECK-LABEL: srai_slli:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 25
+; CHECK-NEXT: srai a0, a0, 31
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 15
+ %3 = sext i16 %sext to i32
+ ret i32 %3
+}
+
+define i32 @srai_slli2(i16 signext %0) {
+; CHECK-LABEL: srai_slli2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 25
+; CHECK-NEXT: srai a0, a0, 30
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 14
+ %3 = sext i16 %sext to i32
+ ret i32 %3
+}
+define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sub_if_uge_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: zext.b a2, a0
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: zext.b a0, a0
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i8 %x, %y
+ %select = select i1 %cmp, i8 0, i8 %y
+ %sub = sub nuw i8 %x, %select
+ ret i8 %sub
+}
+
+define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: sub_if_uge_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: and a1, a1, a2
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i16 %x, %y
+ %select = select i1 %cmp, i16 0, i16 %y
+ %sub = sub nuw i16 %x, %select
+ ret i16 %sub
+}
+
+define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB27_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: j .LBB27_3
+; CHECK-NEXT: .LBB27_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: .LBB27_3:
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: sub a1, a1, a3
+; CHECK-NEXT: sub a1, a1, a4
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, %y
+ %select = select i1 %cmp, i64 0, i64 %y
+ %sub = sub nuw i64 %x, %select
+ ret i64 %sub
+}
+
+define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lw a3, 4(a1)
+; CHECK-NEXT: lw a4, 8(a1)
+; CHECK-NEXT: lw a5, 12(a1)
+; CHECK-NEXT: lw a6, 4(a2)
+; CHECK-NEXT: lw t0, 12(a2)
+; CHECK-NEXT: lw a7, 8(a2)
+; CHECK-NEXT: beq a5, t0, .LBB28_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu t1, a5, t0
+; CHECK-NEXT: j .LBB28_3
+; CHECK-NEXT: .LBB28_2:
+; CHECK-NEXT: sltu t1, a4, a7
+; CHECK-NEXT: .LBB28_3:
+; CHECK-NEXT: lw a1, 0(a1)
+; CHECK-NEXT: lw a2, 0(a2)
+; CHECK-NEXT: beq a3, a6, .LBB28_5
+; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: sltu t2, a3, a6
+; CHECK-NEXT: j .LBB28_6
+; CHECK-NEXT: .LBB28_5:
+; CHECK-NEXT: sltu t2, a1, a2
+; CHECK-NEXT: .LBB28_6:
+; CHECK-NEXT: xor t3, a5, t0
+; CHECK-NEXT: xor t4, a4, a7
+; CHECK-NEXT: or t3, t4, t3
+; CHECK-NEXT: beqz t3, .LBB28_8
+; CHECK-NEXT: # %bb.7:
+; CHECK-NEXT: mv t2, t1
+; CHECK-NEXT: .LBB28_8:
+; CHECK-NEXT: addi t3, t2, -1
+; CHECK-NEXT: and t2, t3, t0
+; CHECK-NEXT: and t0, t3, a2
+; CHECK-NEXT: and t1, t3, a6
+; CHECK-NEXT: sltu a2, a1, t0
+; CHECK-NEXT: and a7, t3, a7
+; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: beq a3, t1, .LBB28_10
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: sltu a6, a3, t1
+; CHECK-NEXT: .LBB28_10:
+; CHECK-NEXT: sub t3, a4, a7
+; CHECK-NEXT: sltu a4, a4, a7
+; CHECK-NEXT: sub a5, a5, t2
+; CHECK-NEXT: sub a3, a3, t1
+; CHECK-NEXT: sub a1, a1, t0
+; CHECK-NEXT: sltu a7, t3, a6
+; CHECK-NEXT: sub a5, a5, a4
+; CHECK-NEXT: sub a4, t3, a6
+; CHECK-NEXT: sub a3, a3, a2
+; CHECK-NEXT: sub a2, a5, a7
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: sw a3, 4(a0)
+; CHECK-NEXT: sw a4, 8(a0)
+; CHECK-NEXT: sw a2, 12(a0)
+; CHECK-NEXT: ret
+ %cmp = icmp ult i128 %x, %y
+ %select = select i1 %cmp, i128 0, i128 %y
+ %sub = sub nuw i128 %x, %select
+ ret i128 %sub
+}
+
+define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a2, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: sll a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %shl = shl i32 %sub, %select
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: minu a2, a0, a2
+; CHECK-NEXT: bltu a0, a1, .LBB30_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: li a0, 4
+; CHECK-NEXT: sll a0, a2, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB30_2:
+; CHECK-NEXT: li a0, 2
+; CHECK-NEXT: sll a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %select2 = select i1 %cmp, i32 2, i32 4
+ %shl = shl i32 %sub, %select2
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: xori a3, a3, 1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: sw a3, 0(a2)
+; CHECK-NEXT: ret
+ %cmp = icmp uge i32 %x, %y
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %select = select i1 %cmp, i32 %y, i32 0
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i8 @sub_if_uge_C_i8(i8 zeroext %x) {
+; CHECK-LABEL: sub_if_uge_C_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -13
+; CHECK-NEXT: zext.b a1, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i8 %x, 12
+ %sub = add i8 %x, -13
+ %conv4 = select i1 %cmp, i8 %sub, i8 %x
+ ret i8 %conv4
+}
+
+define i16 @sub_if_uge_C_i16(i16 zeroext %x) {
+; CHECK-LABEL: sub_if_uge_C_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -251
+; CHECK-NEXT: slli a1, a1, 16
+; CHECK-NEXT: srli a1, a1, 16
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i16 %x, 250
+ %sub = add i16 %x, -251
+ %conv4 = select i1 %cmp, i16 %sub, i16 %x
+ ret i16 %conv4
+}
+
+define i32 @sub_if_uge_C_i32(i32 signext %x) {
+; CHECK-LABEL: sub_if_uge_C_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i64 @sub_if_uge_C_i64(i64 %x) {
+; CHECK-LABEL: sub_if_uge_C_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a2, 1
+; CHECK-NEXT: beq a1, a2, .LBB35_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltiu a2, a1, 2
+; CHECK-NEXT: xori a2, a2, 1
+; CHECK-NEXT: j .LBB35_3
+; CHECK-NEXT: .LBB35_2:
+; CHECK-NEXT: lui a2, 172127
+; CHECK-NEXT: addi a2, a2, 511
+; CHECK-NEXT: sltu a2, a2, a0
+; CHECK-NEXT: .LBB35_3:
+; CHECK-NEXT: neg a2, a2
+; CHECK-NEXT: andi a3, a2, -2
+; CHECK-NEXT: add a1, a1, a3
+; CHECK-NEXT: lui a3, 876449
+; CHECK-NEXT: addi a3, a3, -512
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: sltu a0, a2, a0
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %x, 4999999999
+ %sub = add i64 %x, -5000000000
+ %cond = select i1 %cmp, i64 %sub, i64 %x
+ ret i64 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
+; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: lui a3, 1048560
+; CHECK-NEXT: addi a2, a2, -16
+; CHECK-NEXT: addi a3, a3, 15
+; CHECK-NEXT: sltu a2, a2, a0
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: minu a0, a3, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
+; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 1048560
+; CHECK-NEXT: addi a2, a2, 15
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %sub = add i32 %x, -65521
+ store i32 %sub, ptr %z, align 4
+ %cmp = icmp ugt i32 %x, 65520
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_swapped_i32(i32 %x) {
+; CHECK-LABEL: sub_if_uge_C_swapped_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, 65521
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %x, i32 %sub
+ ret i32 %cond
+}
+
+define i7 @sub_if_uge_C_nsw_i7(i7 %a) {
+; CHECK-LABEL: sub_if_uge_C_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ugt i7 %x, -18
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %add, i7 %x
+ ret i7 %s
+}
+
+define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {
+; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ult i7 %x, -17
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %x, i7 %add
+ ret i7 %s
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
new file mode 100644
index 0000000000000..b45082c351646
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -0,0 +1,963 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define signext i32 @ctlz_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: ctlz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+define signext i32 @log2_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: log2_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: li a1, 31
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
+ %2 = sub i32 31, %1
+ ret i32 %2
+}
+
+define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: log2_ceil_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = sub i32 %a, 1
+ %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
+ %3 = sub i32 32, %2
+ ret i32 %3
+}
+
+define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: findLastSet_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clzw a1, a0
+; CHECK-NEXT: snez a0, a0
+; CHECK-NEXT: xori a1, a1, 31
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
+ %2 = xor i32 31, %1
+ %3 = icmp eq i32 %a, 0
+ %4 = select i1 %3, i32 -1, i32 %2
+ ret i32 %4
+}
+
+define i32 @ctlz_lshr_i32(i32 signext %a) {
+; CHECK-LABEL: ctlz_lshr_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srliw a0, a0, 1
+; CHECK-NEXT: clzw a0, a0
+; CHECK-NEXT: ret
+ %1 = lshr i32 %a, 1
+ %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
+ ret i32 %2
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+
+define i64 @ctlz_i64(i64 %a) nounwind {
+; CHECK-LABEL: ctlz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define signext i32 @cttz_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: cttz_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB6_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
+ ret i32 %1
+}
+
+define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: cttz_zero_undef_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
+ ret i32 %1
+}
+
+define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: findFirstSet_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a2, a0
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: li a2, 64
+; CHECK-NEXT: snez a0, a0
+; CHECK-NEXT: clz a1, a1
+; CHECK-NEXT: sub a2, a2, a1
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: or a0, a0, a2
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
+ %2 = icmp eq i32 %a, 0
+ %3 = select i1 %2, i32 -1, i32 %1
+ ret i32 %3
+}
+
+define signext i32 @ffs_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: ffs_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a2, a0
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: li a2, 65
+; CHECK-NEXT: seqz a0, a0
+; CHECK-NEXT: clz a1, a1
+; CHECK-NEXT: sub a2, a2, a1
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: ret
+ %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
+ %2 = add i32 %1, 1
+ %3 = icmp eq i32 %a, 0
+ %4 = select i1 %3, i32 0, i32 %2
+ ret i32 %4
+}
+
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i64 @cttz_i64(i64 %a) nounwind {
+; CHECK-LABEL: cttz_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beqz a0, .LBB10_2
+; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi a1, a0, -1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: clz a0, a0
+; CHECK-NEXT: li a1, 64
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB10_2:
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
+ ret i64 %1
+}
+
+define signext i32 @sextb_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: sextb_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 24
+ %shr = ashr exact i32 %shl, 24
+ ret i32 %shr
+}
+
+define i64 @sextb_i64(i64 %a) nounwind {
+; CHECK-LABEL: sextb_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.b a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 56
+ %shr = ashr exact i64 %shl, 56
+ ret i64 %shr
+}
+
+define signext i32 @sexth_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: sexth_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i32 %a, 16
+ %shr = ashr exact i32 %shl, 16
+ ret i32 %shr
+}
+
+define i64 @sexth_i64(i64 %a) nounwind {
+; CHECK-LABEL: sexth_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.h a0, a0
+; CHECK-NEXT: ret
+ %shl = shl i64 %a, 48
+ %shr = ashr exact i64 %shl, 48
+ ret i64 %shr
+}
+
+define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: min_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: min a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp slt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @min_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: min_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: min a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp slt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: max_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: max a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @max_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: max_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: max a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: minu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @minu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: minu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {
+; CHECK-LABEL: maxu_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: maxu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %a, %b
+ %cond = select i1 %cmp, i32 %a, i32 %b
+ ret i32 %cond
+}
+
+define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: maxu_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: maxu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %a, %b
+ %cond = select i1 %cmp, i64 %a, i64 %b
+ ret i64 %cond
+}
+
+declare i32 @llvm.abs.i32(i32, i1 immarg)
+
+define i32 @abs_i32(i32 %x) {
+; CHECK-LABEL: abs_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: absw a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+define signext i32 @abs_i32_sext(i32 signext %x) {
+; CHECK-LABEL: abs_i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: absw a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+ ret i32 %abs
+}
+
+declare i64 @llvm.abs.i64(i64, i1 immarg)
+
+define i64 @abs_i64(i64 %x) {
+; CHECK-LABEL: abs_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: abs a0, a0
+; CHECK-NEXT: ret
+ %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
+ ret i64 %abs
+}
+
+declare i32 @llvm.bswap.i32(i32)
+
+define signext i32 @bswap_i32(i32 signext %a) nounwind {
+; CHECK-LABEL: bswap_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: srai a0, a0, 32
+; CHECK-NEXT: ret
+ %1 = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %1
+}
+
+; Similar to bswap_i32 but the result is not sign extended.
+define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {
+; CHECK-LABEL: bswap_i32_nosext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: srli a0, a0, 32
+; CHECK-NEXT: sw a0, 0(a1)
+; CHECK-NEXT: ret
+ %1 = tail call i32 @llvm.bswap.i32(i32 %a)
+ store i32 %1, ptr %x
+ ret void
+}
+
+declare i64 @llvm.bswap.i64(i64)
+
+define i64 @bswap_i64(i64 %a) {
+; CHECK-LABEL: bswap_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rev8 a0, a0
+; CHECK-NEXT: ret
+ %1 = call i64 @llvm.bswap.i64(i64 %a)
+ ret i64 %1
+}
+
+define i64 @srai_slli(i16 signext %0) {
+; CHECK-LABEL: srai_slli:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 57
+; CHECK-NEXT: srai a0, a0, 63
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 15
+ %3 = sext i16 %sext to i64
+ ret i64 %3
+}
+
+define i64 @srai_slli2(i16 signext %0) {
+; CHECK-LABEL: srai_slli2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 57
+; CHECK-NEXT: srai a0, a0, 62
+; CHECK-NEXT: ret
+ %2 = shl i16 %0, 9
+ %sext = ashr i16 %2, 14
+ %3 = sext i16 %sext to i64
+ ret i64 %3
+}
+
+define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 {
+; CHECK-LABEL: func0000000000000001:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: slli a1, a1, 59
+; CHECK-NEXT: srai a1, a1, 63
+; CHECK-NEXT: addw a0, a1, a0
+; CHECK-NEXT: ret
+entry:
+ %2 = shl i8 %1, 3
+ %3 = ashr i8 %2, 7
+ %4 = sext i8 %3 to i32
+ %5 = add nsw i32 %4, %0
+ ret i32 %5
+}
+
+define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
+; RV64I-LABEL: sub_if_uge_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: zext.b a3, a0
+; RV64I-NEXT: sltu a2, a3, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: and a1, a2, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_i8:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: zext.b a2, a0
+; RV64ZBB-NEXT: sub a0, a0, a1
+; RV64ZBB-NEXT: zext.b a0, a0
+; RV64ZBB-NEXT: minu a0, a2, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: zext.b a2, a0
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: zext.b a0, a0
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i8 %x, %y
+ %select = select i1 %cmp, i8 0, i8 %y
+ %sub = sub nuw i8 %x, %select
+ ret i8 %sub
+}
+
+define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
+; RV64I-LABEL: sub_if_uge_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: and a3, a1, a2
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: sltu a2, a2, a3
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: and a1, a2, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_i16:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: zext.h a2, a0
+; RV64ZBB-NEXT: sub a0, a0, a1
+; RV64ZBB-NEXT: zext.h a0, a0
+; RV64ZBB-NEXT: minu a0, a2, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: and a1, a1, a2
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i16 %x, %y
+ %select = select i1 %cmp, i16 0, i16 %y
+ %sub = sub nuw i16 %x, %select
+ ret i16 %sub
+}
+
+define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
+; RV64I-LABEL: sub_if_uge_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: sext.w a3, a0
+; RV64I-NEXT: sltu a2, a3, a2
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: and a1, a2, a1
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.w a2, a0
+; RV64ZBB-NEXT: subw a0, a0, a1
+; RV64ZBB-NEXT: minu a0, a2, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a0
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
+; RV64I-LABEL: sub_if_uge_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a2, a0, a1
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: and a1, a2, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sub a1, a0, a1
+; RV64ZBB-NEXT: minu a0, a0, a1
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, %y
+ %select = select i1 %cmp, i64 0, i64 %y
+ %sub = sub nuw i64 %x, %select
+ ret i64 %sub
+}
+
+define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB36_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: j .LBB36_3
+; CHECK-NEXT: .LBB36_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: .LBB36_3:
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: sub a1, a1, a3
+; CHECK-NEXT: sub a1, a1, a4
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ult i128 %x, %y
+ %select = select i1 %cmp, i128 0, i128 %y
+ %sub = sub nuw i128 %x, %select
+ ret i128 %sub
+}
+
+define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: sltu a2, a3, a2
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %shl = shl i32 %sub, %select
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
+; RV64I-LABEL: sub_if_uge_multiuse_cmp_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: sext.w a3, a0
+; RV64I-NEXT: sltu a4, a3, a2
+; RV64I-NEXT: addi a4, a4, -1
+; RV64I-NEXT: and a1, a4, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: bltu a3, a2, .LBB68_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, 4
+; RV64I-NEXT: sllw a0, a0, a1
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB68_2:
+; RV64I-NEXT: li a1, 2
+; RV64I-NEXT: sllw a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_multiuse_cmp_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.w a2, a1
+; RV64ZBB-NEXT: sext.w a3, a0
+; RV64ZBB-NEXT: subw a0, a0, a1
+; RV64ZBB-NEXT: minu a0, a3, a0
+; RV64ZBB-NEXT: bltu a3, a2, .LBB68_2
+; RV64ZBB-NEXT: # %bb.1:
+; RV64ZBB-NEXT: li a1, 4
+; RV64ZBB-NEXT: sllw a0, a0, a1
+; RV64ZBB-NEXT: ret
+; RV64ZBB-NEXT: .LBB68_2:
+; RV64ZBB-NEXT: li a1, 2
+; RV64ZBB-NEXT: sllw a0, a0, a1
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: minu a0, a3, a0
+; CHECK-NEXT: bltu a3, a2, .LBB38_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: li a1, 4
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB38_2:
+; CHECK-NEXT: li a1, 2
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %select2 = select i1 %cmp, i32 2, i32 4
+ %shl = shl i32 %sub, %select2
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, ptr %z) {
+; RV64I-LABEL: sub_if_uge_multiuse_cmp_store_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltu a3, a0, a1
+; RV64I-NEXT: xori a4, a3, 1
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: sw a4, 0(a2)
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_multiuse_cmp_store_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sltu a3, a0, a1
+; RV64ZBB-NEXT: subw a1, a0, a1
+; RV64ZBB-NEXT: xori a3, a3, 1
+; RV64ZBB-NEXT: minu a0, a0, a1
+; RV64ZBB-NEXT: sw a3, 0(a2)
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: subw a1, a0, a1
+; CHECK-NEXT: xori a3, a3, 1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: sw a3, 0(a2)
+; CHECK-NEXT: ret
+ %cmp = icmp uge i32 %x, %y
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %select = select i1 %cmp, i32 %y, i32 0
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i8 @sub_if_uge_C_i8(i8 zeroext %x) {
+; RV64I-LABEL: sub_if_uge_C_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a1, a0, 13
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: andi a1, a1, -13
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_i8:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: addi a1, a0, -13
+; RV64ZBB-NEXT: zext.b a1, a1
+; RV64ZBB-NEXT: minu a0, a1, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -13
+; CHECK-NEXT: zext.b a1, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i8 %x, 12
+ %sub = add i8 %x, -13
+ %conv4 = select i1 %cmp, i8 %sub, i8 %x
+ ret i8 %conv4
+}
+
+define i16 @sub_if_uge_C_i16(i16 zeroext %x) {
+; RV64I-LABEL: sub_if_uge_C_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sltiu a1, a0, 251
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: andi a1, a1, -251
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_i16:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: addi a1, a0, -251
+; RV64ZBB-NEXT: zext.h a1, a1
+; RV64ZBB-NEXT: minu a0, a1, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a1, a0, -251
+; CHECK-NEXT: slli a1, a1, 48
+; CHECK-NEXT: srli a1, a1, 48
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i16 %x, 250
+ %sub = add i16 %x, -251
+ %conv4 = select i1 %cmp, i16 %sub, i16 %x
+ ret i16 %conv4
+}
+
+define i32 @sub_if_uge_C_i32(i32 signext %x) {
+; RV64I-LABEL: sub_if_uge_C_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: lui a2, 1048560
+; RV64I-NEXT: addi a1, a1, -16
+; RV64I-NEXT: sltu a1, a1, a0
+; RV64I-NEXT: neg a1, a1
+; RV64I-NEXT: addi a2, a2, 15
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a1, 1048560
+; RV64ZBB-NEXT: addi a1, a1, 15
+; RV64ZBB-NEXT: addw a1, a0, a1
+; RV64ZBB-NEXT: minu a0, a1, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: addw a1, a0, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i64 @sub_if_uge_C_i64(i64 %x) {
+; RV64I-LABEL: sub_if_uge_C_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 298
+; RV64I-NEXT: lui a2, 1046192
+; RV64I-NEXT: addi a1, a1, 95
+; RV64I-NEXT: addi a2, a2, -761
+; RV64I-NEXT: slli a1, a1, 12
+; RV64I-NEXT: addi a1, a1, 511
+; RV64I-NEXT: sltu a1, a1, a0
+; RV64I-NEXT: neg a1, a1
+; RV64I-NEXT: slli a2, a2, 9
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a1, 1046192
+; RV64ZBB-NEXT: addi a1, a1, -761
+; RV64ZBB-NEXT: slli a1, a1, 9
+; RV64ZBB-NEXT: add a1, a0, a1
+; RV64ZBB-NEXT: minu a0, a1, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1046192
+; CHECK-NEXT: addi a1, a1, -761
+; CHECK-NEXT: slli a1, a1, 9
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %x, 4999999999
+ %sub = add i64 %x, -5000000000
+ %cond = select i1 %cmp, i64 %sub, i64 %x
+ ret i64 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
+; RV64I-LABEL: sub_if_uge_C_multiuse_cmp_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: lui a3, 1048560
+; RV64I-NEXT: addi a2, a2, -16
+; RV64I-NEXT: sltu a2, a2, a0
+; RV64I-NEXT: neg a4, a2
+; RV64I-NEXT: addi a3, a3, 15
+; RV64I-NEXT: and a3, a4, a3
+; RV64I-NEXT: addw a0, a0, a3
+; RV64I-NEXT: sw a2, 0(a1)
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_multiuse_cmp_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a2, 16
+; RV64ZBB-NEXT: lui a3, 1048560
+; RV64ZBB-NEXT: addi a2, a2, -16
+; RV64ZBB-NEXT: addi a3, a3, 15
+; RV64ZBB-NEXT: sltu a2, a2, a0
+; RV64ZBB-NEXT: addw a3, a0, a3
+; RV64ZBB-NEXT: minu a0, a3, a0
+; RV64ZBB-NEXT: sw a2, 0(a1)
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 16
+; CHECK-NEXT: lui a3, 1048560
+; CHECK-NEXT: addi a2, a2, -16
+; CHECK-NEXT: addi a3, a3, 15
+; CHECK-NEXT: sltu a2, a2, a0
+; CHECK-NEXT: addw a3, a0, a3
+; CHECK-NEXT: minu a0, a3, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, 65520
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, ptr %z, align 4
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
+; RV64I-LABEL: sub_if_uge_C_multiuse_sub_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 1048560
+; RV64I-NEXT: lui a3, 16
+; RV64I-NEXT: addi a2, a2, 15
+; RV64I-NEXT: addw a2, a0, a2
+; RV64I-NEXT: addi a3, a3, -16
+; RV64I-NEXT: sw a2, 0(a1)
+; RV64I-NEXT: bltu a3, a0, .LBB75_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: .LBB75_2:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_multiuse_sub_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a2, 1048560
+; RV64ZBB-NEXT: addi a2, a2, 15
+; RV64ZBB-NEXT: addw a2, a0, a2
+; RV64ZBB-NEXT: minu a0, a2, a0
+; RV64ZBB-NEXT: sw a2, 0(a1)
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a2, 1048560
+; CHECK-NEXT: addi a2, a2, 15
+; CHECK-NEXT: addw a2, a0, a2
+; CHECK-NEXT: minu a0, a2, a0
+; CHECK-NEXT: sw a2, 0(a1)
+; CHECK-NEXT: ret
+ %sub = add i32 %x, -65521
+ store i32 %sub, ptr %z, align 4
+ %cmp = icmp ugt i32 %x, 65520
+ %cond = select i1 %cmp, i32 %sub, i32 %x
+ ret i32 %cond
+}
+
+define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {
+; RV64I-LABEL: sub_if_uge_C_swapped_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: lui a2, 1048560
+; RV64I-NEXT: addi a1, a1, -15
+; RV64I-NEXT: sltu a1, a0, a1
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: addi a2, a2, 15
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_swapped_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: lui a1, 1048560
+; RV64ZBB-NEXT: addi a1, a1, 15
+; RV64ZBB-NEXT: addw a1, a0, a1
+; RV64ZBB-NEXT: minu a0, a0, a1
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_swapped_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048560
+; CHECK-NEXT: addi a1, a1, 15
+; CHECK-NEXT: addw a1, a0, a1
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, 65521
+ %sub = add i32 %x, -65521
+ %cond = select i1 %cmp, i32 %x, i32 %sub
+ ret i32 %cond
+}
+
+define i7 @sub_if_uge_C_nsw_i7(i7 %a) {
+; RV64I-LABEL: sub_if_uge_C_nsw_i7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ori a0, a0, 51
+; RV64I-NEXT: andi a1, a0, 127
+; RV64I-NEXT: sltiu a1, a1, 111
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: andi a1, a1, 17
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_nsw_i7:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: ori a0, a0, 51
+; RV64ZBB-NEXT: andi a1, a0, 127
+; RV64ZBB-NEXT: addi a0, a0, 17
+; RV64ZBB-NEXT: andi a0, a0, 92
+; RV64ZBB-NEXT: minu a0, a0, a1
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a0, a1
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ugt i7 %x, -18
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %add, i7 %x
+ ret i7 %s
+}
+
+define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {
+; RV64I-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ori a0, a0, 51
+; RV64I-NEXT: andi a1, a0, 127
+; RV64I-NEXT: sltiu a1, a1, 111
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: andi a1, a1, 17
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: ori a0, a0, 51
+; RV64ZBB-NEXT: andi a1, a0, 127
+; RV64ZBB-NEXT: addi a0, a0, 17
+; RV64ZBB-NEXT: andi a0, a0, 92
+; RV64ZBB-NEXT: minu a0, a1, a0
+; RV64ZBB-NEXT: ret
+; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori a0, a0, 51
+; CHECK-NEXT: andi a1, a0, 127
+; CHECK-NEXT: addi a0, a0, 17
+; CHECK-NEXT: andi a0, a0, 92
+; CHECK-NEXT: minu a0, a1, a0
+; CHECK-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ult i7 %x, -17
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %x, i7 %add
+ ret i7 %s
+}
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