[llvm] 467a0c3 - [RISCV] Remove remapping Zfinx register classes to GPR class in getRegForInlineAsmConstraint. (#164352)

[via llvm-commits]

Author: Jim Lin
Date: 2025-10-21T13:10:42+08:00
New Revision: 467a0c30a4458b2155f658123ee802ecb91942de

URL: https://github.com/llvm/llvm-project/commit/467a0c30a4458b2155f658123ee802ecb91942de
DIFF: https://github.com/llvm/llvm-project/commit/467a0c30a4458b2155f658123ee802ecb91942de.diff

LOG: [RISCV] Remove remapping Zfinx register classes to GPR class in getRegForInlineAsmConstraint. (#164352)

The codegen for Zfinx has been supported. So we don't need to remap
Zfinx register classes to GPR class.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0a53ba935b1a7..a77d765a8b481 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -24044,18 +24044,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     }
   }
 
-  std::pair<Register, const TargetRegisterClass *> Res =
-      TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
-
-  // If we picked one of the Zfinx register classes, remap it to the GPR class.
-  // FIXME: When Zfinx is supported in CodeGen this will need to take the
-  // Subtarget into account.
-  if (Res.second == &RISCV::GPRF16RegClass ||
-      Res.second == &RISCV::GPRF32RegClass ||
-      Res.second == &RISCV::GPRPairRegClass)
-    return std::make_pair(Res.first, &RISCV::GPRRegClass);
-
-  return Res;
+  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
 InlineAsm::ConstraintCode