[llvm] [AArch64] Widen GPR32 zero cycle zeroing (PR #164244)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 94c3619dd..b74202e70 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5118,8 +5118,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (AArch64::GPR32spRegClass.contains(DestReg) && SrcReg == AArch64::WZR) {
     if (Subtarget.hasZeroCycleZeroingGPR64() &&
         !Subtarget.hasZeroCycleZeroingGPR32()) {
-      MCRegister DestRegX = RI.getMatchingSuperReg(
-            DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
+      MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
+                                                   &AArch64::GPR64spRegClass);
       assert(DestRegX.isValid() && "Destination super-reg not valid");
       BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestRegX)
           .addImm(0)

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https://github.com/llvm/llvm-project/pull/164244