[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Anshil Gandhi via llvm-commits]

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@@ -470,7 +470,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S16, {{Sgpr32Trunc}, {Sgpr32AExt, Sgpr32AExt}})
       .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
       .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
-      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
+      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+      // Split 64-bit add/sub into two 32-bit ops on VGPRs
+      .Uni(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32})
+      .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32})
+      .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}})
+      .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
+
+  addRulesForGOpcs({G_UADDO, G_USUBO, G_UADDE, G_USUBE}, Standard)
+      .Uni(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32}})
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gandhi56 wrote:

I changed the rule so that the operation lives in SGPR for the uniform case. Mapping the carry out bit to `SGPR32Trunc` results in an additional `S1 = G_TRUNC S32` which breaks the assertion that S1 values should not be associated with an SGPR register bank. I had to add some cleanup code after legalization to avoid breaking the assertion. Is that okay or is there a better solution? @petar-avramovic 

https://github.com/llvm/llvm-project/pull/159860