[llvm] Implement hasOrNot (PR #163995)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 322c7b906..1feb749b7 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -828,9 +828,7 @@ public:
   }
 
   /// Return true if the target has a bitwise or-not operation:
-  virtual bool hasOrNot(SDValue X) const {
-    return false;
-  }
+  virtual bool hasOrNot(SDValue X) const { return false; }
 
   /// Return true if the target has a bit-test instruction:
   ///   (X & (1 << Y)) ==/!= 0
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 737471bc9..7f141b669 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12258,8 +12258,8 @@ static SDValue foldVSelectToSignBitSplatMask(SDNode *N, SelectionDAG &DAG) {
   }
 
   // If we have to invert the sign bit mask and OR with -1, only do that
-  // transform if the target has a bitwise 'or not' instruction (the invert is free).
-  // (Cond0 s> -1) ? -1 : N2 --> ~(Cond0 s>> BW-1) | freeze(N2)
+  // transform if the target has a bitwise 'or not' instruction (the invert is
+  // free). (Cond0 s> -1) ? -1 : N2 --> ~(Cond0 s>> BW-1) | freeze(N2)
   if (isAllOnesOrAllOnesSplat(N2) && TLI.hasOrNot(N2)) {
     SDLoc DL(N);
     SDValue ShiftAmt = DAG.getShiftAmountConstant(EltSizeInBits - 1, VT, DL);

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https://github.com/llvm/llvm-project/pull/163995