[llvm] [PowerPC] Implement Context Switch Instr mtlpl (PR #160593)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 17 09:12:42 PDT 2025
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/160593
>From 1b9a17a5d66919cd41baad2630af3ba6b32bd434 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Wed, 24 Sep 2025 19:57:49 +0000
Subject: [PATCH 1/3] [PowerPC] Implement Context Switch Instr mtlpl
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 17 +++++++++++++++++
.../PowerPC/ppc-encoding-ISAFuture.txt | 3 +++
.../PowerPC/ppc64le-encoding-ISAFuture.txt | 3 +++
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 4 ++++
4 files changed, 27 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 1aefea1a1c498..783dec69a6e4c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -182,6 +182,20 @@ class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = XT{5};
}
+class XForm_RBS5<bits<6> opCode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opCode, OOL, IOL, asmstr, itin> {
+
+ bits<5> RB;
+ bits<5> RS;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = RS;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
+}
+
class XX3Form_XTAB6_S<bits<5> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<59, OOL, IOL, asmstr, NoItinerary> {
@@ -294,6 +308,9 @@ let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
"$RT, $L, $RA, $RB", []>;
+ def MTLPL : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
+ "mtlpl $RB, $RS", IIC_SprMTSPR, []>,
+ Requires<[IsPPC64]>;
}
let Predicates = [HasVSX, IsISAFuture] in {
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index cdfc8ce9e0ca5..b53ec3abe62de 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -274,6 +274,9 @@
#CHECK: xvmulhuh 4, 5, 7
0xf0,0x85,0x3b,0xd0
+#CHECK: mtlpl 3, 4
+0x7c,0x80,0x1a,0x26
+
#CHECK: xxmulmul 8, 3, 4, 2
0xed,0x03,0x22,0x08
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index f7e314fc819e4..3a6aeb469d1ea 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -268,6 +268,9 @@
#CHECK: xvmulhuh 4, 5, 7
0xd0,0x3b,0x85,0xf0
+#CHECK: mtlpl 3, 4
+0x26,0x1a,0x80,0x7c
+
#CHECK: xxmulmul 8, 3, 4, 2
0x08,0x22,0x03,0xed
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 29fedd7c20646..f1a2a825fb021 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -387,6 +387,10 @@
#CHECK-BE: xvmulhuh 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0xd0]
#CHECK-LE: xvmulhuh 4, 5, 7 # encoding: [0xd0,0x3b,0x85,0xf0]
+ mtlpl 3, 4
+#CHECK-BE: mtlpl 3, 4 # encoding: [0x7c,0x80,0x1a,0x26]
+#CHECK-LE: mtlpl 3, 4 # encoding: [0x26,0x1a,0x80,0x7c]
+
xxmulmul 8, 3, 4, 2
#CHECK-BE: xxmulmul 8, 3, 4, 2 # encoding: [0xed,0x03,0x22,0x08]
#CHECK-LE: xxmulmul 8, 3, 4, 2 # encoding: [0x08,0x22,0x03,0xed]
>From 6071b76f120629b62462710bb82ef51928291e6b Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 9 Oct 2025 15:58:21 +0000
Subject: [PATCH 2/3] add 32 bit implementation
---
llvm/lib/Target/PowerPC/PPCInstrFuture.td | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 783dec69a6e4c..02312dfc74215 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -308,9 +308,12 @@ let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
"$RT, $L, $RA, $RB", []>;
- def MTLPL : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
- "mtlpl $RB, $RS", IIC_SprMTSPR, []>,
- Requires<[IsPPC64]>;
+ def MTLPL : XForm_RBS5<31, 275, (outs), (ins gprc:$RB, gprc:$RS),
+ "mtlpl $RB, $RS", IIC_SprMTSPR, []>;
+ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+ def MTLPL8 : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
+ "mtlpl $RB, $RS", IIC_SprMTSPR, []>, isPPC64;
+ }
}
let Predicates = [HasVSX, IsISAFuture] in {
>From d4ab6505eec2820debcadb5bba42ff4b1751f87a Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Fri, 17 Oct 2025 16:12:22 +0000
Subject: [PATCH 3/3] add new alias for m[tf]spr 48
---
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 ++
llvm/test/MC/PowerPC/ppc64-encoding-ext.s | 14 ++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index aca7abd5a45a7..44d1a445f82be 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4578,6 +4578,8 @@ def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
+def : InstAlias<"mtpidr $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsISA3_0]>;
+def : InstAlias<"mfpidr $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsISA3_0]>;
foreach SPRG = 4-7 in {
def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
index 959f3c53b0a19..666222028bdf8 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -3491,12 +3491,18 @@
# CHECK-BE: mfamr 2 # encoding: [0x7c,0x5d,0x02,0xa6]
# CHECK-LE: mfamr 2 # encoding: [0xa6,0x02,0x5d,0x7c]
mfamr 2
-# CHECK-BE: mtpid 2 # encoding: [0x7c,0x50,0x0b,0xa6]
-# CHECK-LE: mtpid 2 # encoding: [0xa6,0x0b,0x50,0x7c]
+# CHECK-BE: mtspr 48, 2 # encoding: [0x7c,0x50,0x0b,0xa6]
+# CHECK-LE: mtspr 48, 2 # encoding: [0xa6,0x0b,0x50,0x7c]
mtpid 2
-# CHECK-BE: mfpid 2 # encoding: [0x7c,0x50,0x0a,0xa6]
-# CHECK-LE: mfpid 2 # encoding: [0xa6,0x0a,0x50,0x7c]
+# CHECK-BE: mtspr 48, 2 # encoding: [0x7c,0x50,0x0b,0xa6]
+# CHECK-LE: mtspr 48, 2 # encoding: [0xa6,0x0b,0x50,0x7c]
+ mtpidr 2
+# CHECK-BE: mfspr 2, 48 # encoding: [0x7c,0x50,0x0a,0xa6]
+# CHECK-LE: mfspr 2, 48 # encoding: [0xa6,0x0a,0x50,0x7c]
mfpid 2
+# CHECK-BE: mfspr 2, 48 # encoding: [0x7c,0x50,0x0a,0xa6]
+# CHECK-LE: mfspr 2, 48 # encoding: [0xa6,0x0a,0x50,0x7c]
+ mfpidr 2
# CHECK-BE: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6]
# CHECK-LE: mtlr 2 # encoding: [0xa6,0x03,0x48,0x7c]
mtlr 2
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