[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Craig Topper via llvm-commits]

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@@ -479,6 +490,24 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       ISD::FTRUNC,       ISD::FRINT,         ISD::FROUND,
       ISD::FROUNDEVEN,   ISD::FCANONICALIZE};
 
+  if (Subtarget.hasStdExtP()) {
+    // load/store are already handled by pattern matching
+    SmallVector<MVT, 2> VTs = {MVT::v2i16, MVT::v4i8};
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topperc wrote:

I think the ZIP instructions be used for zero extend. Excerpt from mailing list post https://lists.riscv.org/g/tech-p-ext/message/287

"One important use for the proposed ZIP instructions is to expand
unsigned 8-bit bytes into 16-bit halfwords, and likewise to expand
unsigned 16-bit halfwords into 32-bit words.  If rs2 is x0 and we have

    X(rs1) = A B C D E F G H

then we get the following results:

    ZIP8P     z E z F z G z H
    ZIP8HP    z A z B z C z D

    ZIP16P    z z E F z z G H
    ZIP16HP   z z A B z z C D

where each 'z' is a zero byte (taken from X(rs2), which I said is x0).
"

https://github.com/llvm/llvm-project/pull/162668