[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Petar Avramovic via llvm-commits]

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@@ -470,7 +470,20 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S16, {{Sgpr32Trunc}, {Sgpr32AExt, Sgpr32AExt}})
       .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
       .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
-      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
+      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+      .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}})
+      .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
+      // Split 64-bit add/sub into two 32-bit ops on VGPRs
+      .Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr64}, SplitTo32})
+      .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32});
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petar-avramovic wrote:

Hmm, I see now. SDAG selects V_ADD_U64_PSEUDO and spilts it finalize isel for gfx1200.
For example gfx1250 has V_ADD_U64_e32 which also needs to be supported.
In summary I think we should do same this as sdag for now `.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}});`
no need for doing the split here since it would require some target feature checks

https://github.com/llvm/llvm-project/pull/159860