[llvm] [Hexagon] Handle bitcast of i64 -> v64i1 when Hvx is enabled (PR #163332)

[via llvm-commits]

================
@@ -2024,13 +2026,7 @@ HexagonTargetLowering::LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const {
   // Handle bitcast from i32, v2i16, and v4i8 to v32i1.
   // Splat the input into a 32-element i32 vector, then AND each element
   // with a unique bitmask to isolate individual bits.
-  if (ResTy == MVT::v32i1 &&
-      (ValTy == MVT::i32 || ValTy == MVT::v2i16 || ValTy == MVT::v4i8) &&
-      Subtarget.useHVX128BOps()) {
-    SDValue Val32 = Val;
-    if (ValTy == MVT::v2i16 || ValTy == MVT::v4i8)
-      Val32 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Val);
-
+  auto toV32i1Fromi32 = [&](SDValue Val32) {
     MVT VecTy = MVT::getVectorVT(MVT::i32, 32);
----------------
aankit-ca wrote:

Add an assert to make sure number of bits in Val32 is 32

I would prefer if you do the bitcast to i32 if the input type is not MVT::i32 within the `toV32i1Fromi32` function for easier readability.

Also consider renaming the function to `bitcastToI32`

https://github.com/llvm/llvm-project/pull/163332