[llvm] [NFC][PowerPC] Patch to add the remaining types v2i64, v8i16 and v16i8 into exisiting testfile (PR #163201)
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Wed Oct 15 21:39:36 PDT 2025
https://github.com/Himadhith updated https://github.com/llvm/llvm-project/pull/163201
>From 1f6f366e3d444889b2e190ebdf5516a6d92ea2d2 Mon Sep 17 00:00:00 2001
From: himadhith <himadhith.v at ibm.com>
Date: Mon, 13 Oct 2025 14:07:32 +0000
Subject: [PATCH 1/4] [NFC][PowerPC] Patch to add the remaining types v2i64,
v8i16 and v16i8 into exisiting testfile
---
llvm/test/CodeGen/PowerPC/vector-all-ones.ll | 43 +++++++++++++++++++-
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
index e4c93adcf50a6..18a7276a7639b 100644
--- a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
@@ -11,8 +11,23 @@
; Currently the generated code uses `vspltisw` to generate vector of 1s followed by add operation.
; This pattern is expected to be optimized in a future patch by using `xxleqv` to generate vector of -1s
; followed by subtraction operation.
-define dso_local noundef <4 x i32> @test1(<4 x i32> %a) {
-; CHECK-LABEL: test1:
+
+; Function for the vector type v2i64 `a + {1, 1}`
+define dso_local noundef <2 x i64> @test_v2i64(<2 x i64> noundef %a) {
+; CHECK-LABEL: test_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vspltisw v3, 1
+; CHECK-NEXT: vupklsw v3, v3
+; CHECK-NEXT: vaddudm v2, v2, v3
+; CHECK-NEXT: blr
+entry:
+ %add = add <2 x i64> %a, splat (i64 1)
+ ret <2 x i64> %add
+}
+
+; Function for the vector type v4i32 `a + {1, 1, 1, 1}`
+define dso_local noundef <4 x i32> @test_v4i32(<4 x i32> %a) {
+; CHECK-LABEL: test_v4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltisw v3, 1
; CHECK-NEXT: vadduwm v2, v2, v3
@@ -21,3 +36,27 @@ entry:
%add = add <4 x i32> %a, splat (i32 1)
ret <4 x i32> %add
}
+
+; Function for the vector type v8i16 `a + {1, 1, 1, 1, 1, 1, 1, 1}`
+define dso_local noundef <8 x i16> @test_v8i16(<8 x i16> noundef %a) {
+; CHECK-LABEL: test_v8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vspltish v3, 1
+; CHECK-NEXT: vadduhm v2, v2, v3
+; CHECK-NEXT: blr
+entry:
+ %add = add <8 x i16> %a, splat (i16 1)
+ ret <8 x i16> %add
+}
+
+; Function for the vector type v16i8 `a + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}`
+define dso_local noundef <16 x i8> @test_16i8(<16 x i8> noundef %a) {
+; CHECK-LABEL: test_16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xxspltib v3, 1
+; CHECK-NEXT: vaddubm v2, v2, v3
+; CHECK-NEXT: blr
+entry:
+ %add = add <16 x i8> %a, splat (i8 1)
+ ret <16 x i8> %add
+}
>From 42497b8f666ce5355477f03705edb4709c6fecf4 Mon Sep 17 00:00:00 2001
From: himadhith <himadhith.v at ibm.com>
Date: Tue, 14 Oct 2025 03:51:54 +0000
Subject: [PATCH 2/4] Remove dso_local noundef
---
llvm/test/CodeGen/PowerPC/vector-all-ones.ll | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
index 18a7276a7639b..79704fa9e78ad 100644
--- a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
@@ -13,7 +13,7 @@
; followed by subtraction operation.
; Function for the vector type v2i64 `a + {1, 1}`
-define dso_local noundef <2 x i64> @test_v2i64(<2 x i64> noundef %a) {
+define <2 x i64> @test_v2i64(<2 x i64> %a) {
; CHECK-LABEL: test_v2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltisw v3, 1
@@ -26,7 +26,7 @@ entry:
}
; Function for the vector type v4i32 `a + {1, 1, 1, 1}`
-define dso_local noundef <4 x i32> @test_v4i32(<4 x i32> %a) {
+define <4 x i32> @test_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_v4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltisw v3, 1
@@ -38,7 +38,7 @@ entry:
}
; Function for the vector type v8i16 `a + {1, 1, 1, 1, 1, 1, 1, 1}`
-define dso_local noundef <8 x i16> @test_v8i16(<8 x i16> noundef %a) {
+define <8 x i16> @test_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_v8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltish v3, 1
@@ -50,7 +50,7 @@ entry:
}
; Function for the vector type v16i8 `a + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}`
-define dso_local noundef <16 x i8> @test_16i8(<16 x i8> noundef %a) {
+define <16 x i8> @test_16i8(<16 x i8> %a) {
; CHECK-LABEL: test_16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltib v3, 1
>From 7fba0555faa95905d587057619ba817946bd73a0 Mon Sep 17 00:00:00 2001
From: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: Tue, 14 Oct 2025 11:00:42 +0530
Subject: [PATCH 3/4] Update and rename vector-all-ones.ll to
addition-of-all-ones-vector.ll
---
.../{vector-all-ones.ll => addition-of-all-ones-vector.ll} | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
rename llvm/test/CodeGen/PowerPC/{vector-all-ones.ll => addition-of-all-ones-vector.ll} (88%)
diff --git a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll b/llvm/test/CodeGen/PowerPC/addition-of-all-ones-vector.ll
similarity index 88%
rename from llvm/test/CodeGen/PowerPC/vector-all-ones.ll
rename to llvm/test/CodeGen/PowerPC/addition-of-all-ones-vector.ll
index 79704fa9e78ad..e67d031b1813f 100644
--- a/llvm/test/CodeGen/PowerPC/vector-all-ones.ll
+++ b/llvm/test/CodeGen/PowerPC/addition-of-all-ones-vector.ll
@@ -8,9 +8,7 @@
; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
-; Currently the generated code uses `vspltisw` to generate vector of 1s followed by add operation.
-; This pattern is expected to be optimized in a future patch by using `xxleqv` to generate vector of -1s
-; followed by subtraction operation.
+; The addition of vector `A` with vector of 1s currently uses `vspltisw` to generate vector of 1s followed by add operation.
; Function for the vector type v2i64 `a + {1, 1}`
define <2 x i64> @test_v2i64(<2 x i64> %a) {
>From 0f65d7d474a306b7053edb3efcda4c14f0c6efc4 Mon Sep 17 00:00:00 2001
From: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: Tue, 14 Oct 2025 11:02:11 +0530
Subject: [PATCH 4/4] Rename addition-of-all-ones-vector.ll to
addition-vector-all-ones.ll
---
...addition-of-all-ones-vector.ll => addition-vector-all-ones.ll} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/CodeGen/PowerPC/{addition-of-all-ones-vector.ll => addition-vector-all-ones.ll} (100%)
diff --git a/llvm/test/CodeGen/PowerPC/addition-of-all-ones-vector.ll b/llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll
similarity index 100%
rename from llvm/test/CodeGen/PowerPC/addition-of-all-ones-vector.ll
rename to llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll
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