[llvm] [AArch64] Convert `CSEL(X, 1)` into `CSINC(X, XZR)` in early-ifcvt (PR #162993)

[Csanád Hajdú via llvm-commits]

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@@ -976,6 +1000,14 @@ void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
 
     // Fold the operation. Leave any dead instructions for DCE to clean up.
     if (FoldedOpc) {
+      // NewVReg might be XZR/WZR. In that case create a COPY into a virtual
+      // register.
+      if (!Register::isVirtualRegister(NewVReg)) {
+        unsigned ZeroReg = NewVReg;
+        NewVReg = MRI.createVirtualRegister(RC);
+        BuildMI(MBB, I, DL, get(TargetOpcode::COPY), NewVReg).addReg(ZeroReg);
+      }
+
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Il-Capitano wrote:

Yeah, I'm also not entirely sure on all the requirements for MIR at this point in the pipeline. Looking at the optimization pipeline on compiler explorer, I see that merging XZR/WZR into instructions is done by the register coalescer (https://godbolt.org/z/jxjP6cPPn), which is run after early-ifcvt.

I've run into situations before where using a COPY was preferred at that particular point in the codegen pipeline, so I wanted to be safe here.

https://github.com/llvm/llvm-project/pull/162993