[llvm] ce60a03 - [BranchRelaxation] Fix invalid branch generation in branch-relaxation (#162065)

[via llvm-commits]

Author: sc-clulzze
Date: 2025-10-15T19:31:50+03:00
New Revision: ce60a03573a4d9f28dd6de42f61f0a3c4b0f2be9

URL: https://github.com/llvm/llvm-project/commit/ce60a03573a4d9f28dd6de42f61f0a3c4b0f2be9
DIFF: https://github.com/llvm/llvm-project/commit/ce60a03573a4d9f28dd6de42f61f0a3c4b0f2be9.diff

LOG: [BranchRelaxation] Fix invalid branch generation in branch-relaxation (#162065)

If we have MBB with only one successor which is accessable through both
conditional and unconditional branches (TBB == FBB), in
`fixupConditionalBranch` we will first replace FBB with NewMBB in
successors list - `MBB->replaceSuccessor(FBB, NewBB);`, and then create
branch to TBB - `insertBranch(MBB, &NextBB, TBB, Cond);`, ending up with
two branches to different blocks, but only one successor.

Fixes: https://github.com/llvm/llvm-project/issues/162063

Added: 
    llvm/test/CodeGen/RISCV/branch-rel.mir

Modified: 
    llvm/lib/CodeGen/BranchRelaxation.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index 2d50167faa085..fae952e888b4b 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -491,6 +491,20 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
       return true;
     }
     if (FBB) {
+      // If we get here with a MBB which ends like this:
+      //
+      // bb.1:
+      // successors: %bb.2;
+      // ...
+      // BNE $x1, $x0, %bb.2
+      // PseudoBR %bb.2
+      //
+      // Just remove conditional branch.
+      if (TBB == FBB) {
+        removeBranch(MBB);
+        insertUncondBranch(MBB, TBB);
+        return true;
+      }
       // We need to split the basic block here to obtain two long-range
       // unconditional branches.
       NewBB = createNewBlockAfter(*MBB);

diff  --git a/llvm/test/CodeGen/RISCV/branch-rel.mir b/llvm/test/CodeGen/RISCV/branch-rel.mir
new file mode 100644
index 0000000000000..1ed5f5715a825
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-rel.mir
@@ -0,0 +1,39 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv64 -run-pass=branch-relaxation -o - -verify-machineinstrs | FileCheck %s
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+---
+name:            foo
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $x1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoBR %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $x1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   INLINEASM &".space 4096", 1 /* sideeffect attdialect */
+  ; CHECK-NEXT:   BGE $x1, $x0, %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   PseudoRET
+  bb.0:
+    liveins: $x1
+    BNE $x1, $x0, %bb.3
+    PseudoBR %bb.3
+  bb.1:
+    liveins: $x1
+    INLINEASM &".space 4096", 1
+    BGE $x1, $x0, %bb.3
+  bb.3:
+    PseudoRET
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: